diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-02-02 16:21:02 -0800 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-02-23 09:32:13 -0800 |
| commit | c8f33bd25385f4dc0f1a69e0e9faa04b1941b34e (patch) | |
| tree | b33446710df4ff3bc8b51aa0955315c01bfb80c3 /arch/arm/mach-tegra/Kconfig | |
| parent | d9ecb9be27bb10535159ebb43ca3fa515edfc13b (diff) | |
ARM: tegra: power: Power off multiple CPUs on-line
Currently on Tegra3 cpu complex is powered off in idle (enters CPU0
LP2 state) only if all secondary CPUs are off-line. This commit adds
an option for CPU0 to enter LP2 while secondary CPUs are still on-line
but have been power gated and entered LP2 state by themselves.
The critical race: secondary CPU is waking up from LP2, while CPU0 is
turning common CPU rail off, is addressed as follows.
1. When entering LP2 state on CPU0:
a) disable GIC distributor
b) check that CPU1-3 are all power-gated (i.e., either off-lined or
have entered LP2)
c) if (b) passes - set all interrupts affinity to CPU0, then
re-enable distributor and continue with CPU complex powering off
d) if (b) fails - re-enable distributor and enter clock-gated (LP3)
state on CPU0
This procedure prevents waking secondary CPUs by GIC SPIs.
2. We still need to make sure that no CPU1-3 PPIs from legacy IRQ/FIQ
or private timers would happen. This is achieved by disabling timers
and legacy interrupts if CPU1-3 enters LP2 state with external timers
selected as wake sources. Respectively, establish dependency between
turning rail off and LP2 wake timers configuration options.
3. Finally, no IPIs is sent by CPU0 entering LP2.
There are no special changes in wake up procedures - whenever CPU0
is awaken by external interrupt or wake timer, cpu complex is powered
on by h/w, and secondary CPUs that were in LP2 state are ungated by
the same interrupt (off-line CPUs are kept power gated). Hence, there
is no need for CPU1-3 external wake timers to run while the rail is
off, and these timers are stopped. To make sure that none of secondary
CPUs over-sleeps its LP2 time, CPU0 wake timer is set to minimum sleep
interval of all CPUs.
By default configuration option for powering off multiple on-line CPUs
is disabled on Tegra3.
Change-Id: I4920d0df375536b2b8ebd9e6738c5fe4f92b92a0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/83547
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/Kconfig')
| -rw-r--r-- | arch/arm/mach-tegra/Kconfig | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 0a5d4d930790..2f9205687c88 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -41,7 +41,7 @@ config ARCH_TEGRA_3x_SOC select ARCH_SUPPORTS_MSI if TEGRA_PCI select PCI_MSI if TEGRA_PCI select ARM_ERRATA_754322 - select TEGRA_LP2_ARM_TWD if HAVE_ARM_TWD + select TEGRA_LP2_ARM_TWD if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS help Support for NVIDIA Tegra 3 family of SoCs, based upon the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -475,6 +475,9 @@ config TEGRA_WDT_RECOVERY config TEGRA_LP2_ARM_TWD bool + +config TEGRA_RAIL_OFF_MULTIPLE_CPUS + bool endif config TEGRA_SLOW_CSITE |