diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2016-01-14 00:53:35 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2016-03-21 10:50:55 +0100 |
| commit | 5fc9966aad667f7e4649bb8f74a241492fe3458e (patch) | |
| tree | d17d2521d64dd345db52bc4a0f2151b1005fc1f6 /arch/arm/mach-tegra/board-apalis_t30.h | |
| parent | c8ead507f45de63a125b40096f0d59cb0aaa6780 (diff) | |
apalis_t30: ixora: optionally support leds, switch, foff and wdisable
The Ixora carrier board has a few MXM3 pins repurposed as follows:
Functionality MXM3 Pin
LED4_RED 146
LED4_GREEN 162
LED5_RED 156
LED5_GREEN 152
PCIE1_WDISABLE_N 144
SW3 160
UART2_3_RS232_FOFF_N 164
This patch allows uncommenting an IXORA define in the board header file
in order to make use of those repurposed pins.
Please note that those pins are usually used for the 8-bit MMC/SD slot
aka Apalis MMC1 and the SDHCI controller/driver unfortunately changes
the output driver behaviour in a way preventing any regular GPIO use.
This patch therefore explicitly does not register the SDHCI driver on
this controller instance in the Ixora case to avoid this.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-apalis_t30.h')
| -rw-r--r-- | arch/arm/mach-tegra/board-apalis_t30.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-apalis_t30.h b/arch/arm/mach-tegra/board-apalis_t30.h index c08ff32741b8..14e003453fa7 100644 --- a/arch/arm/mach-tegra/board-apalis_t30.h +++ b/arch/arm/mach-tegra/board-apalis_t30.h @@ -102,6 +102,21 @@ #define WAKE1_MICO TEGRA_GPIO_PV1 +/* + * Uncomment to use MXM3 pins 144, 146, 152, 156, 160, 162 & 164 for LEDs, + * PCIE1_WDISABLE_N, SW3 and UART2_3_RS232_FOFF_N on Ixora carrier board + */ +//#define IXORA +#ifdef IXORA +#define LED4_GREEN TEGRA_GPIO_PB6 +#define LED4_RED TEGRA_GPIO_PB4 +#define LED5_GREEN TEGRA_GPIO_PD0 +#define LED5_RED TEGRA_GPIO_PD3 +#define PCIE1_WDISABLE_N TEGRA_GPIO_PB5 +#define SW3 TEGRA_GPIO_PB7 +#define UART2_3_RS232_FOFF_N TEGRA_GPIO_PV3 +#endif /* IXORA */ + /* STMPE811 IRQs */ #define STMPE811_IRQ_BASE TEGRA_NR_IRQS #define STMPE811_IRQ_END (STMPE811_IRQ_BASE + 22) |