diff options
| author | Nitin Kumbhar <nkumbhar@nvidia.com> | 2012-03-02 17:10:03 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-03-02 23:19:55 -0800 |
| commit | 92cdd7b1d0674004fdccd2a13e7e0a6dfdcf972b (patch) | |
| tree | 5f88b03b3190c77f0e106c58ff51b554d96d86d4 /arch/arm/mach-tegra/board-cardhu-memory.c | |
| parent | 5a7f8d38015b177b3350eb07231df1d1405a6754 (diff) | |
arm: tegra: cardhu: increase mc outstanding reqs for lower ram freqs
The number of outstanding memory transactions is limited by a setting
in MC. This leads to dc underflows which cause flickers on lcd panel.
Increase the limits to optimal values which don't show dc underflows.
Currently, the cap on outstanding requests for a frequency is calculated
by linearly scaling up values for frequencies keeping minimum value at
0x08. An exception has to be made to resolve dc underflows and
lcd flickers.
For cardhu, the lower ram frequencies are 25.5MHz, 51MHz and 102MHz.
So increase minimum value to 0x10 and set 0x18 for 102MHz as an optimal
value with which there are no dc underflows.
Memory tables of Hynix-1GB, Hynix-2GB and Samsung-2GB memory types are
updated with this change.
Bug 932113
Bug 946316
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on:http://git-master/r/87230
(cherry picked from commit 39642475dc4401e666d4ade338c5b9e0741ce017)
Change-Id: I19e8c04f4acc93f07121ee7da98588d2441147e8
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/87236
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Edward Ahn <eahn@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-cardhu-memory.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-cardhu-memory.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c index 4b009888d165..a2492b147155 100644 --- a/arch/arm/mach-tegra/board-cardhu-memory.c +++ b/arch/arm/mach-tegra/board-cardhu-memory.c @@ -706,7 +706,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x80000280, /* EMC_DYN_SELF_REF_CONTROL */ 0x00020001, /* MC_EMEM_ARB_CFG */ - 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ @@ -826,7 +826,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000001, /* MC_EMEM_ARB_CFG */ - 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ @@ -946,7 +946,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000001, /* MC_EMEM_ARB_CFG */ - 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ @@ -2149,7 +2149,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ 0x00010001, /* MC_EMEM_ARB_CFG */ - 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ @@ -2269,7 +2269,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000001, /* MC_EMEM_ARB_CFG */ - 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ @@ -2752,7 +2752,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ 0x00020001, /* MC_EMEM_ARB_CFG */ - 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ @@ -2872,7 +2872,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ 0x00010001, /* MC_EMEM_ARB_CFG */ - 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ @@ -2992,7 +2992,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000001, /* MC_EMEM_ARB_CFG */ - 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ |