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authorJin Park <jinyoungp@nvidia.com>2011-10-10 17:42:17 +0900
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:50:10 -0800
commit3b194497f996c5c6c25c183cf76c4fbd291ba32c (patch)
tree3b46e512231f201884826f6ad530bf1342e146ac /arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c
parent0b76311abd082346aa2091c1b4c6dfa7454067cb (diff)
arm: tegra: cardhu: pm298: Correct min_uV for SD1 power rail
Previously it is configured SD1 min_uV to 1.05V to avoid voltage under-shooting issue on SD1 power rail. But it doesn't need after safe voltage scaling step patch for max77663 regulator driver. Reviewed-on: http://git-master/r/56962 (cherry picked from commit 3ea4ea8a5594cb8b5781bfd06816993b0a3e90cf) Change-Id: Ied2b8e54f2ac05182b1e0d256e48cda2b6aab0b4 Signed-off-by: Jin Park <jinyoungp@nvidia.com> Reviewed-on: http://git-master/r/65064 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rd4e1d0ea5f087fe223bb8bb5722c972031012678
Diffstat (limited to 'arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c')
-rw-r--r--arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c b/arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c
index 5adefecb3ed3..eb51e4e26ba6 100644
--- a/arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c
+++ b/arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c
@@ -199,9 +199,7 @@ static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
MAX77663_PDATA_INIT(sd0, 600000, 3387500, NULL, 1, 0, 0,
0, 0, -1, FPS_SRC_NONE, -1, -1, EN2_CTRL_SD0 | SD_FSRADE_DISABLE);
-/* FIXME: MAX77663 Rev.3 has voltage undershooting issue when voltage scaling.
- * To prevent system hang, SD1 min_uV was configured to 1050000. */
-MAX77663_PDATA_INIT(sd1, 1050000, 1587500, NULL, 1, 0, 0,
+MAX77663_PDATA_INIT(sd1, 800000, 1587500, NULL, 1, 0, 0,
1, 1, -1, FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
MAX77663_PDATA_INIT(sd2, 600000, 3387500, NULL, 1, 0, 0,