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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2012-12-12 16:04:46 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2012-12-12 16:04:46 +0100
commit97f194075b5c332a941751552b467547d7a3ab0a (patch)
tree40a748e26886433d7631c6c2d5bb119a7c805d04 /arch/arm/mach-tegra/board-colibri_t20-panel.c
parentab52fcd9bf5aea752cbd4933921e2c63ee5bf069 (diff)
colibri_t20: fix hsync/vsync polarity for default VESA VGA
VESA VGA mode defines hsync/vsync to be of polarity low rather than high.
Diffstat (limited to 'arch/arm/mach-tegra/board-colibri_t20-panel.c')
-rw-r--r--arch/arm/mach-tegra/board-colibri_t20-panel.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/board-colibri_t20-panel.c b/arch/arm/mach-tegra/board-colibri_t20-panel.c
index 21a992252922..6cb83ce29cf5 100644
--- a/arch/arm/mach-tegra/board-colibri_t20-panel.c
+++ b/arch/arm/mach-tegra/board-colibri_t20-panel.c
@@ -328,11 +328,11 @@ static struct tegra_fb_data colibri_t20_hdmi_fb_data = {
static struct tegra_dc_out_pin colibri_t20_dc_out_pins[] = {
{
.name = TEGRA_DC_OUT_PIN_H_SYNC,
- .pol = TEGRA_DC_OUT_PIN_POL_HIGH,
+ .pol = TEGRA_DC_OUT_PIN_POL_LOW,
},
{
.name = TEGRA_DC_OUT_PIN_V_SYNC,
- .pol = TEGRA_DC_OUT_PIN_POL_HIGH,
+ .pol = TEGRA_DC_OUT_PIN_POL_LOW,
},
{
.name = TEGRA_DC_OUT_PIN_PIXEL_CLOCK,