arm: tegra: thermal: new ATE rev and margins

Added check for new ATE rev (0.9+).
Added WAR for ATE revs 0.9-0.11 - continue to use PLL-TSOSC for thermals.

Updated thermal thresholds and CPU and GPU EDP margins per thermal
margins spreadsheet.

Bug 1429685
Bug 1510809
Bug 1511626

Change-Id: I78528be0ed6b01625dd464054fbbf39c810c8873
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/407793
Reviewed-by: Automatic_Commit_Validation_User

1 files changed, 80 insertions, 29 deletions

diff --git a/arch/arm/mach-tegra/board-norrin-power.c b/arch/arm/mach-tegra/board-norrin-power.c
index 4afd7c760b9f..300dc6475fbf 100644
--- a/arch/arm/mach-tegra/board-norrin-power.c
+++ b/arch/arm/mach-tegra/board-norrin-power.c
@@ -183,18 +183,43 @@ static struct tegra_thermtrip_pmic_data tpdata_as3722 = {
 	.poweroff_reg_data = 0x2,
 };
 
+/* This is really v2 rev of the norrin_soctherm_data structure */
 static struct soctherm_platform_data norrin_soctherm_data = {
 	.therm = {
 		[THERM_CPU] = {
 			.zone_enable = true,
 			.passive_delay = 1000,
-			.hotspot_offset = 6000,
+			.hotspot_offset = 10000,
+			.num_trips = 3,
+			.trips = {
+				{
+					.cdev_type = "tegra-shutdown",
+					.trip_temp = 105000,
+					.trip_type = THERMAL_TRIP_CRITICAL,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+				{
+					.cdev_type = "tegra-heavy",
+					.trip_temp = 102000,
+					.trip_type = THERMAL_TRIP_HOT,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+				{
+					.cdev_type = "cpu-balanced",
+					.trip_temp = 92000,
+					.trip_type = THERMAL_TRIP_PASSIVE,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+			},
 			.tzp = &soctherm_tzp,
 		},
 		[THERM_GPU] = {
 			.zone_enable = true,
 			.passive_delay = 1000,
-			.hotspot_offset = 6000,
+			.hotspot_offset = 5000,
 			.num_trips = 3,
 			.trips = {
 				{
@@ -213,7 +238,7 @@ static struct soctherm_platform_data norrin_soctherm_data = {
 				},
 				{
 					.cdev_type = "gpu-balanced",
-					.trip_temp = 90000,
+					.trip_temp = 89000,
 					.trip_type = THERMAL_TRIP_PASSIVE,
 					.upper = THERMAL_NO_LIMIT,
 					.lower = THERMAL_NO_LIMIT,
@@ -237,26 +262,57 @@ static struct soctherm_platform_data norrin_soctherm_data = {
 		},
 		[THERM_PLL] = {
 			.zone_enable = true,
+			.tzp = &soctherm_tzp,
+		},
+	},
+	.throttle = {
+		[THROTTLE_HEAVY] = {
+			.priority = 100,
+			.devs = {
+				[THROTTLE_DEV_CPU] = {
+					.enable = true,
+					.depth = 80,
+					.throttling_depth = "heavy_throttling",
+				},
+				[THROTTLE_DEV_GPU] = {
+					.enable = true,
+					.throttling_depth = "heavy_throttling",
+				},
+			},
+		},
+	},
+};
+
+/* Only the diffs from norrin_soctherm_data structure */
+static struct soctherm_platform_data norrin_v1_soctherm_data = {
+	.therm = {
+		[THERM_CPU] = {
+			.zone_enable = true,
+			.passive_delay = 1000,
+			.hotspot_offset = 10000,
+		},
+		[THERM_PLL] = {
+			.zone_enable = true,
 			.passive_delay = 1000,
 			.num_trips = 3,
 			.trips = {
 				{
 					.cdev_type = "tegra-shutdown",
-					.trip_temp = 99000,
+					.trip_temp = 97000,
 					.trip_type = THERMAL_TRIP_CRITICAL,
 					.upper = THERMAL_NO_LIMIT,
 					.lower = THERMAL_NO_LIMIT,
 				},
 				{
 					.cdev_type = "tegra-heavy",
-					.trip_temp = 96000,
+					.trip_temp = 94000,
 					.trip_type = THERMAL_TRIP_HOT,
 					.upper = THERMAL_NO_LIMIT,
 					.lower = THERMAL_NO_LIMIT,
 				},
 				{
 					.cdev_type = "cpu-balanced",
-					.trip_temp = 86000,
+					.trip_temp = 84000,
 					.trip_type = THERMAL_TRIP_PASSIVE,
 					.upper = THERMAL_NO_LIMIT,
 					.lower = THERMAL_NO_LIMIT,
@@ -265,46 +321,41 @@ static struct soctherm_platform_data norrin_soctherm_data = {
 			.tzp = &soctherm_tzp,
 		},
 	},
-	.throttle = {
-		[THROTTLE_HEAVY] = {
-			.priority = 100,
-			.devs = {
-				[THROTTLE_DEV_CPU] = {
-					.enable = true,
-					.depth = 80,
-					.throttling_depth = "heavy_throttling",
-				},
-				[THROTTLE_DEV_GPU] = {
-					.enable = true,
-					.throttling_depth = "heavy_throttling",
-				},
-			},
-		},
-	},
 };
 
 int __init norrin_soctherm_init(void)
 {
+	const int t13x_cpu_edp_temp_margin = 5000,
+		t13x_gpu_edp_temp_margin = 6000;
+	int cp_rev, ft_rev;
 	struct board_info pmu_board_info;
 	struct board_info board_info;
-	enum soctherm_therm_id therm_cpu;
+	enum soctherm_therm_id therm_cpu = THERM_CPU;
 
 	tegra_get_board_info(&board_info);
 
-	/* For T132 platforms: ATE rev check (TODO) */
-	therm_cpu = THERM_PLL;
+	cp_rev = tegra_fuse_calib_base_get_cp(NULL, NULL);
+	ft_rev = tegra_fuse_calib_base_get_ft(NULL, NULL);
+
+	if (cp_rev) {
+		/* ATE rev is Old or Mid - use PLLx sensor only */
+		norrin_soctherm_data.therm[THERM_CPU] =
+			norrin_v1_soctherm_data.therm[THERM_CPU];
+		norrin_soctherm_data.therm[THERM_PLL] =
+			norrin_v1_soctherm_data.therm[THERM_PLL];
+		therm_cpu = THERM_PLL; /* override CPU with PLL zone */
+	}
 
 	/* do this only for supported CP,FT fuses */
-	if ((tegra_fuse_calib_base_get_cp(NULL, NULL) >= 0) &&
-	    (tegra_fuse_calib_base_get_ft(NULL, NULL) >= 0)) {
+	if ((cp_rev >= 0) && (ft_rev >= 0)) {
 		tegra_platform_edp_init(
 			norrin_soctherm_data.therm[therm_cpu].trips,
 			&norrin_soctherm_data.therm[therm_cpu].num_trips,
-			7000); /* edp temperature margin */
+			t13x_cpu_edp_temp_margin);
 		tegra_platform_gpu_edp_init(
 			norrin_soctherm_data.therm[THERM_GPU].trips,
 			&norrin_soctherm_data.therm[THERM_GPU].num_trips,
-			7000);
+			t13x_gpu_edp_temp_margin);
 		tegra_add_cpu_vmax_trips(
 			norrin_soctherm_data.therm[therm_cpu].trips,
 			&norrin_soctherm_data.therm[therm_cpu].num_trips);