diff options
author | Mohit Kataria <mkataria@nvidia.com> | 2012-05-18 17:28:04 +0530 |
---|---|---|
committer | Varun Colbert <vcolbert@nvidia.com> | 2012-07-05 15:38:10 -0700 |
commit | e764753820cb723501692204d8d36c5103903a2c (patch) | |
tree | 0600fc0fe5941ce29756258d05461472a74bf95b /arch/arm/mach-tegra/board-p1852-pinmux.c | |
parent | 25033fb96283a8ba9018db9ec13b64ace8022101 (diff) |
ARM: Tegra: p1852: changed pinmux settings
Pinmux updated as per the latest pinmux sheet.
Bug 978870
Change-Id: I122439df3d043216f1c8c2c1a0a3c88e74d760ee
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/111573
(cherry picked from commit 4e65d7d21b5ac5b25e3563ce6a7eb50cf1d8128d)
Reviewed-on: http://git-master/r/103340
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-p1852-pinmux.c')
-rw-r--r-- | arch/arm/mach-tegra/board-p1852-pinmux.c | 122 |
1 files changed, 88 insertions, 34 deletions
diff --git a/arch/arm/mach-tegra/board-p1852-pinmux.c b/arch/arm/mach-tegra/board-p1852-pinmux.c index 8d5edb066817..21f310b0ef16 100644 --- a/arch/arm/mach-tegra/board-p1852-pinmux.c +++ b/arch/arm/mach-tegra/board-p1852-pinmux.c @@ -170,6 +170,21 @@ static __initdata struct tegra_drive_pingroup_config p1852_drive_pinmux[] = { .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ } +/* For LV(Low voltage) pad groups which has IO_RESET bit */ +#define LVPAD_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ + } + + + static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { /* SDMMC1 pinmux */ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), @@ -191,14 +206,6 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(KB_ROW8, SDMMC2, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_ROW9, SDMMC2, PULL_UP, NORMAL, INPUT), - /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, PULL_UP, NORMAL, INPUT), - /* SDMMC4 pinmux */ DEFAULT_PINMUX(CAM_MCLK, POPSDMMC4, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PCC1, POPSDMMC4, NORMAL, NORMAL, INPUT), @@ -210,6 +217,7 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(GPIO_PBB5, POPSDMMC4, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PBB6, POPSDMMC4, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PBB7, POPSDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, POPSDMMC4, PULL_UP, NORMAL, INPUT), /* UART1 pinmux */ DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT), @@ -228,10 +236,10 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), /* UART5 pinmux */ - DEFAULT_PINMUX(SDMMC4_DAT0, UARTE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SDMMC4_DAT1, UARTE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT2, UARTE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT3, UARTE, NORMAL, NORMAL, OUTPUT), + LVPAD_PINMUX(SDMMC4_DAT0, UARTE, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT1, UARTE, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT2, UARTE, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT3, UARTE, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), /* I2C1 pinmux */ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), @@ -261,6 +269,12 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(ULPI_DATA6, SPI2, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA7, SPI2, NORMAL, NORMAL, INPUT), + /* SPI3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK, SPI3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SPI3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SPI3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SPI3, NORMAL, NORMAL, INPUT), + /* SPDIF pinmux */ DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), @@ -277,10 +291,10 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), /* DAP3 */ - DEFAULT_PINMUX(SDMMC4_DAT4, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT5, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT6, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT7, I2S4, NORMAL, NORMAL, INPUT), + LVPAD_PINMUX(SDMMC4_DAT4, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT5, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT6, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT7, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), /* NOR pinmux */ DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, INPUT), @@ -299,8 +313,8 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(GMI_AD13, GMI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_AD14, GMI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_AD15, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_ADV_N, GMI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_CLK, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_CS0_N, GMI, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_OE_N, GMI, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_RST_N, GMI, NORMAL, NORMAL, OUTPUT), @@ -376,6 +390,8 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, PULL_DOWN, NORMAL, INPUT), + VI_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), @@ -387,18 +403,37 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { VI_PINMUX(VI_PCLK, VI, PULL_UP, TRISTATE, INPUT, DISABLE, DISABLE), /* pin config for gpios */ - DEFAULT_PINMUX(VI_D0, SAFE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_OUT, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_REQ, RSVD2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_SCK, SPI5, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI2_CS1_N, SPI2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPDIF_OUT, SAFE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO, SAFE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D0, SAFE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT, SAFE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS2_N, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_VSYNC, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, NORMAL, NORMAL, INPUT), + LVPAD_PINMUX(SDMMC4_CLK, NAND, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, RSVD0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPI2_CS1_N, SPI2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, TRISTATE, INPUT), }; int __init p1852_pinmux_init(void) @@ -418,18 +453,37 @@ int __init p1852_pinmux_init(void) } static struct gpio_init_pin_info p1852_sku8_gpios[] = { - - GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW4, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PT4, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PEE2, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PZ4, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD2, false, 1), - GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD1, false, 1), - GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD0, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD0, true, 0), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW3, true, 0), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK5, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX5, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX6, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX7, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV0, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV1, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV6, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV7, true, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN4, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN6, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW1, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PB2, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PC1, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PC6, true, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PZ2, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN5, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD3, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV2, true, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV3, true, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD4, true, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC4, false, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PA7, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PB4, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD5, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN7, true, 0), }; int __init p1852_gpio_init(void) |