diff options
| author | Rakesh Bodla <rbodla@nvidia.com> | 2012-06-07 17:29:15 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-06-07 18:16:31 -0700 |
| commit | b17f01f41b5cd2a49e48b87fb51d59c181819d89 (patch) | |
| tree | 19a003bcb9f0a9025c6ebbae3af7eb8e97cce29a /arch/arm/mach-tegra/board-p1852.c | |
| parent | 51457b0dc10527b1b1a28028e3891e81b840b92d (diff) | |
ARM: tegra3: usb: USB1_UTMIP_XCVR_CFG0_0 value changed
Changed USB1_UTMIP_XCVR_CFG0_0 register value with values
provided by sys-eng
* Implemented algo as described on Bug 974236
* Added variable 'usb_calib_mask' in 'usb platform data' to
make distinction on how many bits to mask in usb_calib_0 fuse
Bug 978870
Bug 972436
Change-Id: I71f27b0cf5ffe33a9896238b01c52650ca632352
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/103308
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-p1852.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-p1852.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index eebbb24a9871..044c7a4815ff 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -367,11 +367,12 @@ static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { .idle_wait_delay = 17, .elastic_limit = 16, .term_range_adj = 6, - .xcvr_setup = 15, - .xcvr_setup_offset = 0, + .xcvr_setup = 63, + .xcvr_setup_offset = 6, .xcvr_use_fuses = 1, .xcvr_lsfslew = 2, .xcvr_lsrslew = 2, + .xcvr_use_lsb = 1, }, }; @@ -392,11 +393,12 @@ static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = { .idle_wait_delay = 17, .elastic_limit = 16, .term_range_adj = 6, - .xcvr_setup = 15, - .xcvr_setup_offset = 0, + .xcvr_setup = 63, + .xcvr_setup_offset = 6, .xcvr_use_fuses = 1, .xcvr_lsfslew = 2, .xcvr_lsrslew = 2, + .xcvr_use_lsb = 1, }, }; @@ -417,11 +419,12 @@ static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { .idle_wait_delay = 17, .elastic_limit = 16, .term_range_adj = 6, - .xcvr_setup = 8, - .xcvr_setup_offset = 0, + .xcvr_setup = 63, + .xcvr_setup_offset = 6, .xcvr_use_fuses = 1, .xcvr_lsfslew = 2, .xcvr_lsrslew = 2, + .xcvr_use_lsb = 1, }, }; |