ARM: tegra: clock: Synchronize Tegra3 clocks scaling

On Tegra3 clocks of major h/w engines - 2D/EPP/3D/MPE/VDE/SE - are
sourced from PLLC through integer dividers. Low resolution of these
dividers does not allow to set scaling frequency levels matching
intermediate voltage steps within core voltage range. Only changing
the source frequency can achieve it. However, re-locking common PLL
while engines are running requires synchronization of engines clock
control, and complex operations including switching to backup sources
during PLL stabilization time.

This commit introduces a new virtual clock "cbus" to support clocks
synchronization and PLLC re-locking procedures. The dvfs table for
cbus clock is constructed from frequency steps close to maximum rates
for each characterized core voltage level. Engine clocks exposed to
the drivers are no longer physical module clocks, but shared cbus
users. Setting the rate for such clock specifies the clock floor.
The final cbus rate is determined as maximum floor setting for all
enabled engines, and rounded up along the cbus dvfs ladder. Actual
engine clock rate is set equal to the cbus clock rate. Hence, engines
will be running close to maximum frequency for minimum voltage that
satisfies all floor requests.

Special case: Host1x. This clock will be always configured at 1/2 of
cbus clock rate, and its shared user floor request is ignored by cbus
target frequency calculations.

Added cbus dvfs tables and updated VDE engine dvfs data.

Original-Change-Id: Ic02ea08227f920dc4f47b2389c311a23cea472f6
Reviewed-on: http://git-master/r/36199
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R1b7556f1cca12987e4f7c8c6342778da1cec1915

1 files changed, 3 insertions, 2 deletions

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 65d92e1bca1a..294c289b6a21 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -359,7 +359,7 @@ int clk_set_parent(struct clk *c, struct clk *parent)
 	 * setting enable clock while setting parent.
 	 */
 	if ((c->refcnt == 0) && (c->flags & MUX)) {
-		pr_warn("Setting parent of clock %s with refcnt 0", c->name);
+		pr_debug("Setting parent of clock %s with refcnt 0\n", c->name);
 		disable = true;
 		ret = clk_enable_locked(c);
 		if (ret)
@@ -427,7 +427,7 @@ int clk_set_rate_locked(struct clk *c, unsigned long rate)
 	 */
 	if ((c->refcnt == 0) && (c->flags & (DIV_U71 | DIV_U16)) &&
 		clk_is_auto_dvfs(c)) {
-		pr_warn("Setting rate of clock %s with refcnt 0", c->name);
+		pr_debug("Setting rate of clock %s with refcnt 0\n", c->name);
 		disable = true;
 		ret = clk_enable_locked(c);
 		if (ret)
@@ -639,6 +639,7 @@ void __init tegra_init_max_rate(struct clk *c, unsigned long max_rate)
 	c->max_rate = max_rate;
 	list_for_each_entry(shared_bus_user,
 			    &c->shared_bus_list, u.shared_bus_user.node) {
+		shared_bus_user->u.shared_bus_user.rate = max_rate;
 		shared_bus_user->max_rate = max_rate;
 	}
 }