diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-07-14 20:11:04 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:14:23 -0700 |
| commit | 795d2d5a2b3f7ca475431ac0b0e9254ec535e397 (patch) | |
| tree | ffdf0aadb294c16e83d0a6c6888eede21189577a /arch/arm/mach-tegra/clock.h | |
| parent | f37cdda6b76267b86c90d2142f539b2c56b132c0 (diff) | |
ARM: tegra: clock: Reduce Tegra3 pll post-lock delay
Reduced pll post-lock delay from 50us to 2us.
Rearranged wait for lock loop to delay first check of lock bit
by 2us after pll is enabled.
Added read fence for PLLM lock via PMC (in this case enable bit is
in APB bus register, but lock detect bit is in PPSB bus register).
Bug 1017271
Change-Id: Ibc963533854383e884d87be61e1b98e9d54d3ea0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/115933
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Rebase-Id: R4b90af965e631dbd0e6437946d61809836c7306d
Diffstat (limited to 'arch/arm/mach-tegra/clock.h')
| -rw-r--r-- | arch/arm/mach-tegra/clock.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 56e69092c33f..7a140a7f87df 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -43,7 +43,7 @@ struct clk; #define USE_PLL_LOCK_BITS 1 /* Use lock bits for PLL stabiliation */ #define USE_PLLE_SS 1 /* Use spread spectrum coefficients for PLLE */ #ifdef CONFIG_ARCH_TEGRA_3x_SOC -#define PLL_POST_LOCK_DELAY 50 /* Safety delay after lock is detected */ +#define PLL_POST_LOCK_DELAY 2 /* Safety delay after lock is detected */ #else #define PLL_POST_LOCK_DELAY 10 /* Safety delay after lock is detected */ #endif |