diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-07-14 20:11:04 -0700 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-07-23 10:29:54 -0700 |
| commit | 8ecf3112449b1b34d16de9545a6af50c766d30f4 (patch) | |
| tree | fc49ea7a9d61c1f302e3a720fecf065cf239281e /arch/arm/mach-tegra/clock.h | |
| parent | e67927dd092fec85d4026f1e19b42b47266b4208 (diff) | |
ARM: tegra: clock: Reduce Tegra3 pll post-lock delay
Reduced pll post-lock delay from 50us to 2us.
Rearranged wait for lock loop to delay first check of lock bit
by 2us after pll is enabled.
Added read fence for PLLM lock via PMC (in this case enable bit is
in APB bus register, but lock detect bit is in PPSB bus register).
Bug 1017271
Change-Id: Ibc963533854383e884d87be61e1b98e9d54d3ea0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/115933
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/clock.h')
| -rw-r--r-- | arch/arm/mach-tegra/clock.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index c27176b1cc0d..888808461bb9 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -27,7 +27,7 @@ #else #define USE_PLL_LOCK_BITS 1 /* Use lock bits for PLL stabiliation */ #define USE_PLLE_SS 1 /* Use spread spectrum coefficients for PLLE */ -#define PLL_POST_LOCK_DELAY 50 /* Safety delay after lock is detected */ +#define PLL_POST_LOCK_DELAY 2 /* Safety delay after lock is detected */ #endif #define DIV_BUS (1 << 0) |