diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-01-12 20:27:55 -0800 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2012-01-30 11:46:15 -0800 |
| commit | e818b6ec2c0ab3bf142291983eb0f2840f62570c (patch) | |
| tree | 35c95cfb6b57ac9b31eab7128f38b3d9533627a7 /arch/arm/mach-tegra/common.c | |
| parent | e43a17627f3e7151170082660040d9679c5fa9b1 (diff) | |
ARM: tegra: clock: Auto-detect PLLP rate in clock init
Tegra3 platform may boot with one of the predefined fixed PLLP
(peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This
commit implements auto-detection of PLLP rate, as well as CPU,
and system bus PLLP dependencies configuration during clock tree
initialization.
Bug 928260
Change-Id: I65ea4db2e5cfe96f13566c93e882a3be9deaa129
Reviewed-on: http://git-master/r/75850
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77295
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 2acf4bdcef94..74ea22cf2efb 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -2,7 +2,7 @@ * arch/arm/mach-tegra/common.c * * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2010-2012 NVIDIA Corporation * * Author: * Colin Cross <ccross@android.com> @@ -148,10 +148,10 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "2d", "pll_c", 0, false }, { "3d", "pll_c", 0, false }, #else - { "pll_p", NULL, 408000000, true }, - { "pll_p_out1", "pll_p", 9600000, false }, + { "pll_p", NULL, 0, true }, + { "pll_p_out1", "pll_p", 0, false }, { "pll_p_out2", "pll_p", 48000000, false }, - { "pll_p_out3", "pll_p", 102000000, true }, + { "pll_p_out3", "pll_p", 0, true }, { "pll_m_out1", "pll_m", 275000000, false }, { "pll_p_out4", "pll_p", 102000000, false }, { "sclk", "pll_p_out4", 102000000, true }, |