diff options
author | Kasoju Mallikarjun <mkasoju@nvidia.com> | 2010-07-29 23:07:05 +0530 |
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committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2010-08-06 12:10:01 -0700 |
commit | 785fb21c5b0de6cfa4cc9bb40e6a8717d6fffa07 (patch) | |
tree | dd950611eee89fb84d0e94dca5d784acf56f1230 /arch/arm/mach-tegra/common.c | |
parent | 313ac68a3f78d4bbe728eb499e1faf8720d33d93 (diff) |
[arm/tegra]AES: Disabling custom SSK support for AP20 AO3 chip
AP20 A03 LP0 WAR cannot support custom SSK. So, disabling
customer SSK support for AP20 AO3 chip.
Bug 714957
Change-Id: I14b21b55aae878d43be7c76584ae58af10883c13
Reviewed-on: http://git-master/r/4551
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Phillip Smith <psmith@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r-- | arch/arm/mach-tegra/common.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index a1bc52ddce0d..85b61f337e3e 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -32,6 +32,11 @@ #include "board.h" #define APB_MISC_HIDREV 0x804 +#define FUSE_VISIBILITY_REG_OFFSET 0x48 +#define FUSE_VISIBILITY_BIT_POS 28 +#define FUSE_SPARE_BIT_18_REG_OFFSET 0x248 +#define FUSE_SPARE_BIT_19_REG_OFFSET 0x24c + bool tegra_chip_compare(u32 chip, u32 major_rev, u32 minor_rev) { @@ -46,6 +51,28 @@ bool tegra_chip_compare(u32 chip, u32 major_rev, u32 minor_rev) (major_rev==major || major_rev==TEGRA_ALL_REVS); } +bool tegra_is_ap20_a03p(void) +{ + if (tegra_is_ap20_a03()) { + void __iomem *clk = IO_ADDRESS(TEGRA_CLK_RESET_BASE); + void __iomem *fuse = IO_ADDRESS(TEGRA_FUSE_BASE); + u32 clk_val = readl(clk + FUSE_VISIBILITY_REG_OFFSET); + u32 fuse_18_val = 0; + u32 fuse_19_val = 0; + + clk_val |= (1 << FUSE_VISIBILITY_BIT_POS); + writel(clk_val, (clk + FUSE_VISIBILITY_REG_OFFSET)); + fuse_18_val = readl(fuse + FUSE_SPARE_BIT_18_REG_OFFSET); + fuse_19_val = readl(fuse + FUSE_SPARE_BIT_19_REG_OFFSET); + clk_val &= ~(1 << FUSE_VISIBILITY_BIT_POS); + writel(clk_val, (clk + FUSE_VISIBILITY_REG_OFFSET)); + return (((fuse_18_val|fuse_19_val)&1)? true:false); + } + else { + return false; + } +} + #ifdef CONFIG_DMABOUNCE int dma_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) { |