diff options
author | Sanjay Singh Rawat <srawat@nvidia.com> | 2012-04-16 18:33:26 +0530 |
---|---|---|
committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-04-19 04:49:05 -0700 |
commit | ae081534395f749f880ce4f3ad72e65aa9a1cf72 (patch) | |
tree | 19aa9f485d3a8cea10a1b5faf8e78195d801fb40 /arch/arm/mach-tegra/common.c | |
parent | f561fa95a9158dabd459e0956f74065cedc3ac5a (diff) |
arm: tegra: resolve compilation time warnings
Bug 949219
Change-Id: I875f8688a272c415ebf345b8f30e4afdf7551b29
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/91523
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r-- | arch/arm/mach-tegra/common.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index a1f1aebb5b24..779897729c9d 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -298,8 +298,6 @@ void tegra_init_cache(bool init) { void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; u32 aux_ctrl; - u32 speedo; - u32 tmp; #ifdef CONFIG_TRUSTED_FOUNDATIONS /* issue the SMC to enable the L2 */ @@ -326,6 +324,8 @@ void tegra_init_cache(bool init) writel(0x221, p + L2X0_TAG_LATENCY_CTRL); writel(0x221, p + L2X0_DATA_LATENCY_CTRL); } else { + u32 speedo; + /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */ speedo = tegra_cpu_speedo_id(); if (speedo == 4 || speedo == 5 || speedo == 6 || @@ -348,6 +348,8 @@ void tegra_init_cache(bool init) if (init) { l2x0_init(p, aux_ctrl, 0x8200c3fe); } else { + u32 tmp; + tmp = aux_ctrl; aux_ctrl = readl(p + L2X0_AUX_CTRL); aux_ctrl &= 0x8200c3fe; |