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authorJuha Tukkinen <jtukkinen@nvidia.com>2012-04-10 13:53:21 +0300
committerRohan Somvanshi <rsomvanshi@nvidia.com>2012-04-12 23:34:09 -0700
commitb3a62d3e5c820ed3569a9cb2226025cd1046d0ed (patch)
tree3964c4fba57b269fca098938d8979be1132a5c24 /arch/arm/mach-tegra/common.c
parent5e5343ef05f7168ef49b57f95dbf6289f88a76f7 (diff)
ARM: tegra: common: Remove T30 A01 SMMU workaround
Remove CONFIG_TEGRA_SMMU_BASE_AT_E0000000 workaround as T30 A01 is no longer supported. Change-Id: I0ba6c838984e3c3ec401057925727c9596a8075f Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/95644 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r--arch/arm/mach-tegra/common.c52
1 files changed, 0 insertions, 52 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index a3a870efc7e0..a1f1aebb5b24 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -775,28 +775,9 @@ out:
iounmap(to_io);
}
-#ifdef CONFIG_TEGRA_SMMU_BASE_AT_E0000000
-#define FORCE_SMMU_BASE_FOR_TEGRA3_A01 1
-#else
-#define FORCE_SMMU_BASE_FOR_TEGRA3_A01 0
-#endif
-#if FORCE_SMMU_BASE_FOR_TEGRA3_A01 || \
- (defined(CONFIG_TEGRA_IOVMM_SMMU) && defined(CONFIG_ARCH_TEGRA_3x_SOC))
-/* Support for Tegra3 A01 chip mask that needs to have SMMU IOVA reside in
- * the upper half of 4GB IOVA space. A02 and after use the bottom 1GB and
- * do not need to reserve memory.
- */
-#define SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
-#endif
-
void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
unsigned long fb2_size)
{
-#ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
- int smmu_reserved = 0;
- struct tegra_smmu_window *smmu_window = tegra_smmu_window(0);
-#endif
-
if (carveout_size) {
tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
if (memblock_remove(tegra_carveout_start, carveout_size)) {
@@ -842,33 +823,6 @@ void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
tegra_grhost_aperture = tegra_carveout_start;
-#ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
- if (!smmu_window) {
- pr_err("No SMMU resource\n");
- } else {
- size_t smmu_window_size;
-
- if (FORCE_SMMU_BASE_FOR_TEGRA3_A01 ||
- (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3 &&
- tegra_get_revision() == TEGRA_REVISION_A01)) {
- smmu_window->start = TEGRA_SMMU_BASE_TEGRA3_A01;
- smmu_window->end = TEGRA_SMMU_BASE_TEGRA3_A01 +
- TEGRA_SMMU_SIZE_TEGRA3_A01 - 1;
- }
- smmu_window_size = smmu_window->end + 1 - smmu_window->start;
- if (smmu_window->start >= 0x80000000) {
- if (memblock_reserve(smmu_window->start,
- smmu_window_size))
- pr_err(
- "Failed to reserve SMMU I/O VA window %08lx@%08lx\n",
- (unsigned long)smmu_window_size,
- (unsigned long)smmu_window->start);
- else
- smmu_reserved = 1;
- }
- }
-#endif
-
if (tegra_lp0_vec_size &&
(tegra_lp0_vec_start < memblock_end_of_DRAM())) {
if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
@@ -922,12 +876,6 @@ void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
tegra_vpr_start,
tegra_vpr_size ?
tegra_vpr_start + tegra_vpr_size - 1 : 0);
-
-#ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
- if (smmu_reserved)
- pr_info("SMMU: %08lx - %08lx\n",
- smmu_window->start, smmu_window->end);
-#endif
}
static struct resource ram_console_resources[] = {