diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-04-09 17:13:14 -0700 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-04-12 23:07:23 -0700 |
| commit | cdcc11d678fbd043a4567a12877727e36dab3f0a (patch) | |
| tree | 4fda43f950b461f1ff4349fe7b3d1d4a10b0987c /arch/arm/mach-tegra/common.c | |
| parent | 0acbb8c934be8bf8f1fcfbd7ef527e62c5a5cb00 (diff) | |
ARM: tegra: clock: Update common clock table
- Moved table entries for always running core clocks on the top of
the table (this way we guarantee that changing parent of such clock
down the road would automatically enable new parent).
- Removed unnecessary pll_a and pll_a_out0 entries (effectively they
are "NOP") - actual audio configuration is done in per-board tables.
- Removed unnecessary pll_c and pll_c_out1 entries for emulation
platforms
Change-Id: I8327d6313804419405dd93af08f369db02fcbf25
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/95465
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 4786aced9c57..a3a870efc7e0 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -153,6 +153,11 @@ static int max_cpu_current; static __initdata struct tegra_clk_init_table common_clk_init_table[] = { /* name parent rate enabled */ { "clk_m", NULL, 0, true }, + { "emc", NULL, 0, true }, + { "cpu", NULL, 0, true }, + { "kfuse", NULL, 0, true }, + { "fuse", NULL, 0, true }, + { "sclk", NULL, 0, true }, #ifdef CONFIG_TEGRA_SILICON_PLATFORM #ifdef CONFIG_ARCH_TEGRA_2x_SOC { "pll_p", NULL, 216000000, true }, @@ -199,24 +204,16 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "sclk", "pll_p_out4", 108000000, true }, { "hclk", "sclk", 108000000, true }, { "pclk", "hclk", 54000000, true }, - { "pll_c", NULL, ULONG_MAX, false }, - { "pll_c_out1", "pll_c", 208000000, false }, #endif #ifdef CONFIG_TEGRA_SLOW_CSITE { "csite", "clk_m", 1000000, true }, #else { "csite", NULL, 0, true }, #endif - { "emc", NULL, 0, true }, - { "cpu", NULL, 0, true }, - { "kfuse", NULL, 0, true }, - { "fuse", NULL, 0, true }, { "pll_u", NULL, 480000000, false }, { "sdmmc1", "pll_p", 48000000, false}, { "sdmmc3", "pll_p", 48000000, false}, { "sdmmc4", "pll_p", 48000000, false}, - { "pll_a", "pll_p_out1", 0, false}, - { "pll_a_out0", "pll_a", 0, false}, #ifndef CONFIG_ARCH_TEGRA_2x_SOC { "cbus", "pll_c", 416000000, false }, { "pll_c_out1", "pll_c", 208000000, false }, |