diff options
| author | Hiro Sugawara <hsugawara@nvidia.com> | 2011-12-13 09:12:26 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2011-12-21 12:06:25 +0530 |
| commit | 510eb104d5b09aed924d009ff9462dd5f50f7ff4 (patch) | |
| tree | 445234e03b7d062199cce1b650e350ca9ad9d42b /arch/arm/mach-tegra/common.c | |
| parent | bc569fe2bd2ba6abeebbafa0e04a3f1dc23a1dc6 (diff) | |
arm: tegra: smmu: Add config option to force Tegra3 A01 IOVA range
For debugging and working around SMMU/AVP IOVA range issues.
Default is "n" for production IOVA range.
Also removed chip revision knowledge from AVP loader.
Change-Id: I69984feaebe93a1d05d018ecf8a6e79d18bb0087
Reviewed-on: http://git-master/r/69515
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index a58f8cc625a0..c2a61d661a31 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -741,18 +741,24 @@ out: iounmap(to_io); } -#ifdef CONFIG_TEGRA_IOVMM_SMMU +#ifdef CONFIG_TEGRA_SMMU_BASE_AT_E0000000 +#define FORCE_SMMU_BASE_FOR_TEGRA3_A01 1 +#else +#define FORCE_SMMU_BASE_FOR_TEGRA3_A01 0 +#endif +#if FORCE_SMMU_BASE_FOR_TEGRA3_A01 || \ + (defined(CONFIG_TEGRA_IOVMM_SMMU) && defined(CONFIG_ARCH_TEGRA_3x_SOC)) /* Support for Tegra3 A01 chip mask that needs to have SMMU IOVA reside in * the upper half of 4GB IOVA space. A02 and after use the bottom 1GB and * do not need to reserve memory. */ -#define SUPPORT_TEGRA_3_IOVMM_SMMU_A01 +#define SUPPORT_SMMU_BASE_FOR_TEGRA3_A01 #endif void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size, unsigned long fb2_size) { -#ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01 +#ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01 int smmu_reserved = 0; struct tegra_smmu_window *smmu_window = tegra_smmu_window(0); #endif @@ -802,16 +808,18 @@ void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size, if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture) tegra_grhost_aperture = tegra_carveout_start; -#ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01 +#ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01 if (!smmu_window) { pr_err("No SMMU resource\n"); } else { size_t smmu_window_size; - if (tegra_get_revision() == TEGRA_REVISION_A01) { - smmu_window->start = TEGRA_SMMU_BASE_A01; - smmu_window->end = TEGRA_SMMU_BASE_A01 + - TEGRA_SMMU_SIZE_A01 - 1; + if (FORCE_SMMU_BASE_FOR_TEGRA3_A01 || + (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3 && + tegra_get_revision() == TEGRA_REVISION_A01)) { + smmu_window->start = TEGRA_SMMU_BASE_TEGRA3_A01; + smmu_window->end = TEGRA_SMMU_BASE_TEGRA3_A01 + + TEGRA_SMMU_SIZE_TEGRA3_A01 - 1; } smmu_window_size = smmu_window->end + 1 - smmu_window->start; if (smmu_window->start >= 0x80000000) { @@ -881,7 +889,7 @@ void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size, tegra_vpr_size ? tegra_vpr_start + tegra_vpr_size - 1 : 0); -#ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01 +#ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01 if (smmu_reserved) pr_info("SMMU: %08lx - %08lx\n", smmu_window->start, smmu_window->end); |