diff options
| author | Diwakar Tundlam <dtundlam@nvidia.com> | 2011-12-02 15:49:42 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2011-12-08 18:08:51 +0530 |
| commit | f4ca296f90a173c299194a57f259f4c58952f0f5 (patch) | |
| tree | 6ee9d6b9f198092b3a05a6ba3ab6affe1a9f35e1 /arch/arm/mach-tegra/common.c | |
| parent | 4180067cd919d5258bf47b619a5c7c90a1c209cd (diff) | |
arm: tegra: Set G-CPU L2 cache latency based on chip sku
Bug 909628
Change-Id: I945c3fe7675cf481b770be7025d436b6bf4e9ee6
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/68073
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 642d0aea76a8..21ffbe44ed76 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -262,6 +262,7 @@ void tegra_init_cache(bool init) #ifdef CONFIG_CACHE_L2X0 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; u32 aux_ctrl; + u32 speedo; #ifdef CONFIG_TRUSTED_FOUNDATIONS /* issue the SMC to enable the L2 */ @@ -288,9 +289,15 @@ void tegra_init_cache(bool init) writel(0x221, p + L2X0_TAG_LATENCY_CTRL); writel(0x221, p + L2X0_DATA_LATENCY_CTRL); } else { - /* FIXME: This should be based on speedo id. */ - writel(0x442, p + L2X0_TAG_LATENCY_CTRL); - writel(0x552, p + L2X0_DATA_LATENCY_CTRL); + /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */ + speedo = tegra_cpu_speedo_id(); + if (speedo == 4 || speedo == 5 || speedo == 6) { + writel(0x442, p + L2X0_TAG_LATENCY_CTRL); + writel(0x552, p + L2X0_DATA_LATENCY_CTRL); + } else { + writel(0x441, p + L2X0_TAG_LATENCY_CTRL); + writel(0x551, p + L2X0_DATA_LATENCY_CTRL); + } } #else writel(0x770, p + L2X0_TAG_LATENCY_CTRL); |