diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-01-05 17:53:39 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:49:06 -0700 |
| commit | 6a7d0bbdfb3d0bfb177e18e8302e292dd7b8c078 (patch) | |
| tree | 140caf75b2644f54c07348658e0060e01fdb534e /arch/arm/mach-tegra/cortex-a9.S | |
| parent | 9c9f938f2c7d141a19668fe663cf186baca7f573 (diff) | |
arm: tegra: Add Tegra3 cluster-dependent PL310 timing values
The tag and data RAM latency values for the PL310 L2 cache controller
are different between the G and LP CPU clusters. Set the correct
cluster-dependent value whenever initializing or re-initializing
the L2 cache controller.
Original-Change-Id: I7681ebec58eaff293577269a85c51994140b1e34
Reviewed-on: http://git-master/r/15082
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I3f637783b52930f1d9303e044b645c7d136efc70
Diffstat (limited to 'arch/arm/mach-tegra/cortex-a9.S')
| -rw-r--r-- | arch/arm/mach-tegra/cortex-a9.S | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S index 1b2287033a4b..9fe221a097c6 100644 --- a/arch/arm/mach-tegra/cortex-a9.S +++ b/arch/arm/mach-tegra/cortex-a9.S @@ -538,6 +538,17 @@ ENTRY(__cortex_a9_l2x0_restart) mov32 r9, (TEGRA_ARM_PL310_BASE-IO_CPU_PHYS+IO_CPU_VIRT) add r10, r8, #CTX_L2_CTRL ldmia r10, {r3-r7} +#ifdef CONFIG_ARCH_TEGRA_3x_SOC +#ifndef CONFIG_TEGRA_FPGA_PLATFORM + mov32 r5, (TEGRA_FLOW_CTRL_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT) + ldr r5, [r5, #0x2C] @ FLOW_CTRL_CLUSTER_CONTROL + ands r5, r5, #1 @ 0 == G cluster, 1 == LP cluster + movweq r5, #0x331 @ G tag + movweq r6, #0x441 @ G data + movwne r5, #0x221 @ LP tag + movwne r6, #0x221 @ LP data +#endif +#endif #ifndef CONFIG_TRUSTED_FOUNDATIONS str r5, [r9, #L2X0_TAG_LATENCY_CTRL] str r6, [r9, #L2X0_DATA_LATENCY_CTRL] @@ -546,7 +557,6 @@ ENTRY(__cortex_a9_l2x0_restart) mov r4, #0x2 @ L2X0_DYNAMIC_CLK_GATING_EN str r4, [r9, #L2X0_PWR_CTRL] cmp r0, #0 - beq __reenable_l2x0 mov r0, #0xff |