diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-03-28 12:01:12 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:54:33 -0700 |
| commit | d2c569be96204a3bcd843e5040b1b5c636728816 (patch) | |
| tree | de382441627524d5540bac8dcc3970cd24369b90 /arch/arm/mach-tegra/cortex-a9.S | |
| parent | 9ea9dce375e0b842048897a16d3cd01601b66279 (diff) | |
ARM: tegra: power: Force FW bit when SMP is enabled.
Force FW bit in CP15 auxiliary control register during resume from low power
mode if SMP bit in the same register is set. On Tegra3 in LP mode FW bit is
always zero, even though SMP bit is retained. Hence, this change properly
recovers FW bit on return from ULP to G-mode.
Bug 807595
Original-Change-Id: I5f5149797bbd8050300d5d3e72006c72234a65d8
Reviewed-on: http://git-master/r/24534
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I1c8536bf4f0b57ba45c1b7508b8adfb2e22c88a4
Diffstat (limited to 'arch/arm/mach-tegra/cortex-a9.S')
| -rw-r--r-- | arch/arm/mach-tegra/cortex-a9.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S index a4c1c19a2c6c..76dd9f7656e8 100644 --- a/arch/arm/mach-tegra/cortex-a9.S +++ b/arch/arm/mach-tegra/cortex-a9.S @@ -405,6 +405,8 @@ ENTRY(__cortex_a9_restore) mcr p15, 2, r0, c0, c0, 0 @ csselr mcr p15, 0, r1, c1, c0, 0 @ sctlr + tst r2, #(0x1 << 6) + orrne r2, r2, #(1 << 0) @ sync FW bit with SMP state mcr p15, 0, r2, c1, c0, 1 @ actlr #ifndef CONFIG_TRUSTED_FOUNDATIONS //TL : moved to secure |