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authorAlex Frid <afrid@nvidia.com>2011-12-14 15:28:44 -0800
committerRohan Somvanshi <rsomvanshi@nvidia.com>2012-01-19 10:29:49 -0800
commit4f5892b1c1aa1ffb085333bb2412464a66910a99 (patch)
treec89dc27e341342176a60a8531385526c133de2b1 /arch/arm/mach-tegra/cpu-tegra.c
parent732dd0ebfa107da83c18bedc42f1d606271bb89c (diff)
ARM: tegra: dvfs: Add cold zone Tegra3 CPU dvfs limits
Added alternative frequency limits for Tegra3 CPU. These limits are applied only in the lowest CPU EDP temperature zone, and the offset from regular Tegra3 dvfs frequencies is set at -50MHz at all scaling voltage steps. Offset values as well as temperature threshold are to be updated per characterization. Bug 913884 Change-Id: Ia420f54b4c9fdc966e44d0269d45d9164d751b5f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/70189 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/75615 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/cpu-tegra.c')
-rw-r--r--arch/arm/mach-tegra/cpu-tegra.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 5599c298ac5b..24ed5d229a5d 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -41,6 +41,7 @@
#include "clock.h"
#include "cpu-tegra.h"
+#include "dvfs.h"
/* tegra throttling and edp governors require frequencies in the table
to be in ascending order */
@@ -226,11 +227,14 @@ int tegra_edp_update_thermal_zone(int temperature)
mutex_lock(&tegra_cpu_lock);
edp_thermal_index = index;
- /* Update cpu rate if cpufreq (at least on cpu0) is already started */
+ /* Update cpu rate if cpufreq (at least on cpu0) is already started;
+ alter cpu dvfs table for this thermal zone if necessary */
+ tegra_cpu_dvfs_alter(edp_thermal_index, true);
if (target_cpu_speed[0]) {
edp_update_limit();
tegra_cpu_set_speed_cap(NULL);
}
+ tegra_cpu_dvfs_alter(edp_thermal_index, false);
mutex_unlock(&tegra_cpu_lock);
return ret;