ARM: tegra2: power: Fix reset race condition between the CPUs

During LP2 for CPU idle on Tegra2, there could be a race condition
between the CPUs. CPU1 cannot autonomously shut itself down (put
itself into reset). CPU1 must be reset by CPU0 but only when it
has no outstanding memory or I/O transactions going on (i.e., it
is in the WFI state). CPU1 indicates its readiness to be reset
by setting status in a PMC scratch register. If CPU1 wakes up
and CPU0 sees CPU1's ready to be reset status before CPU1 can
clear it CPU1 could be reset at inappropriate times resulting
in loss of cache coherency and ultimately a kernel panic.

Eliminate the race condition by ensuring that:

- CPU1's reset ready status is cleared as early as possible
  before CPU1 rejoins the coherent world.
- Use writel when updating the IRAM LP2 status flags to ensure
  the IRAM and coherent memory views of the flags are consistent.
- If there is not enough time remaining for CPU1 to be in LP2 for
  the minimum residency time, clear CPU1's reset status flag
  before entering WFI so that CPU0 will not wait for CPU1 to be
  ready to reset (since it won't be if there is insufficient time).

Change-Id: I20dc5c6406b1521f20852294d48ce6d67f0926b9
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd485f696126d7ca019d15651b839d4f2fc595848

1 files changed, 27 insertions, 7 deletions

diff --git a/arch/arm/mach-tegra/cpuidle-t2.c b/arch/arm/mach-tegra/cpuidle-t2.c
index 034c8bbce1a8..14fde6f7c4ab 100644
--- a/arch/arm/mach-tegra/cpuidle-t2.c
+++ b/arch/arm/mach-tegra/cpuidle-t2.c
@@ -71,6 +71,9 @@ static inline unsigned int time_to_bin(unsigned int time)
 
 #ifdef CONFIG_SMP
 
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX	0x4C
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR	0x344
+
 static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
 static s64 tegra_cpu1_wake_by_time = LLONG_MAX;
@@ -79,6 +82,7 @@ static int tegra2_reset_sleeping_cpu(int cpu)
 {
 	int ret = 0;
 
+	BUG_ON(cpu == 0);
 	BUG_ON(cpu == smp_processor_id());
 	tegra_pen_lock();
 
@@ -96,38 +100,51 @@ static void tegra2_wake_reset_cpu(int cpu)
 {
 	u32 reg;
 
+	BUG_ON(cpu == 0);
+	BUG_ON(cpu == smp_processor_id());
+
+	tegra_pen_lock();
+
+	tegra2_cpu_clear_resettable();
+
 	/* enable cpu clock on cpu */
 	reg = readl(clk_rst + 0x4c);
-	writel(reg & ~(1 << (8 + cpu)), clk_rst + 0x4c);
+	writel(reg & ~(1 << (8 + cpu)),
+	       clk_rst + CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
 
 	/* take the CPU out of reset */
 	reg = 0x1111 << cpu;
-	writel(reg, clk_rst + 0x344);
+	writel(reg, clk_rst +
+	       CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
 
 	/* unhalt the cpu */
 	flowctrl_writel(0, FLOW_CTRL_HALT_CPU(1));
+
+	tegra_pen_unlock();
 }
 
 static int tegra2_reset_other_cpus(int cpu)
 {
 	int i;
-	int abort = -1;
+	int ret = 0;
+
+	BUG_ON(cpu != 0);
 
 	for_each_online_cpu(i) {
 		if (i != cpu) {
 			if (tegra2_reset_sleeping_cpu(i)) {
-				abort = i;
+				ret = -EBUSY;
 				break;
 			}
 		}
 	}
 
-	if (abort >= 0) {
+	if (ret) {
 		for_each_online_cpu(i) {
-			if (i != cpu && i < abort)
+			if (i != cpu)
 				tegra2_wake_reset_cpu(i);
 		}
-		return -EINVAL;
+		return ret;
 	}
 
 	return 0;
@@ -249,6 +266,7 @@ static void tegra2_idle_lp2_cpu_1(struct cpuidle_device *dev,
 		/*
 		 * Not enough time left to enter LP2
 		 */
+		tegra2_cpu_clear_resettable();
 		tegra_cpu_wfi();
 		return;
 	}
@@ -263,6 +281,8 @@ static void tegra2_idle_lp2_cpu_1(struct cpuidle_device *dev,
 
 	tegra2_sleep_wfi(PLAT_PHYS_OFFSET - PAGE_OFFSET);
 
+	tegra2_cpu_clear_resettable();
+
 	tegra_cpu1_wake_by_time = LLONG_MAX;
 
 	tegra_twd_resume(&twd_context);