diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-04-18 21:35:58 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:32 -0800 |
| commit | 59c7b7b5b71f1b7328e0ae29c069a4d4888b712e (patch) | |
| tree | 648f43d2f88d4dc17ec51fa752087d72c150520e /arch/arm/mach-tegra/cpuidle.c | |
| parent | 11119f27d5051bb676f302f9b5759d1c2997917a (diff) | |
ARM: tegra: power: Set minimum LP2 target residency
Added board level tuning parameter to specify minimum LP2 residency
time (previous policy allows down to zero residency targets limited
only by LP2 exit latency).
Original-Change-Id: I4ae7d458fba78f35a40f138cf9489bf938715b22
Reviewed-on: http://git-master/r/28162
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I38e798ca6d242d136ea2353d90cc961de14f25b6
Rebase-Id: Rcf9efce3dd037b0a7ca13a9c342f884fac38d654
Diffstat (limited to 'arch/arm/mach-tegra/cpuidle.c')
| -rw-r--r-- | arch/arm/mach-tegra/cpuidle.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 4f975fb72be1..465b8aa1fbc1 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -3,7 +3,7 @@ * * CPU idle driver for Tegra CPUs * - * Copyright (c) 2010, NVIDIA Corporation. + * Copyright (c) 2010-2011, NVIDIA Corporation. * Copyright (c) 2011 Google, Inc. * Author: Colin Cross <ccross@android.com> * Gary King <gking@nvidia.com> @@ -58,6 +58,8 @@ static struct { unsigned int last_lp2_int_count[NR_IRQS]; } idle_stats; +static unsigned int tegra_lp2_min_residency; + struct cpuidle_driver tegra_idle = { .name = "tegra_idle", .owner = THIS_MODULE, @@ -115,6 +117,8 @@ static int tegra_idle_enter_lp2(struct cpuidle_device *dev, hrtimer_peek_ahead_timers(); smp_rmb(); + if (state->target_residency < tegra_lp2_min_residency) + state->target_residency = tegra_lp2_min_residency; idle_stats.cpu_wants_lp2_time[dev->cpu] += us; @@ -143,6 +147,8 @@ static int tegra_idle_enter(unsigned int cpu) dev->state_count = 0; dev->cpu = cpu; + tegra_lp2_min_residency = tegra_cpu_lp2_min_residency(); + state = &dev->states[0]; snprintf(state->name, CPUIDLE_NAME_LEN, "LP3"); snprintf(state->desc, CPUIDLE_DESC_LEN, "CPU flow-controlled"); @@ -161,6 +167,8 @@ static int tegra_idle_enter(unsigned int cpu) state->target_residency = tegra_cpu_power_off_time() + tegra_cpu_power_good_time(); + if (state->target_residency < tegra_lp2_min_residency) + state->target_residency = tegra_lp2_min_residency; state->power_usage = 0; state->flags = CPUIDLE_FLAG_TIME_VALID; state->enter = tegra_idle_enter_lp2; |