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authorScott Williams <scwilliams@nvidia.com>2011-06-29 11:45:53 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:42:49 -0800
commitf944d3f344ca055c0bbba80010ca2b6786c27bb3 (patch)
treec3eb29d3e11ef7f6c3722c3f2e9139b2c6221671 /arch/arm/mach-tegra/delay.S
parent150a0bd861b0032f0272d982a00b2e980b94d417 (diff)
ARM: tegra: power: Prefer movw/movt for loading addresses
The movw/movt instruction pair (encapsulated by the mov32 macro) is preferred over literals for loading addresses. The use of literals for singleton data accesses can cause unnecessary cache misses and evictions for cache lines that are unlikely to be accessed again in the near future. Furthermore, certain code sequences must refrain from using data accesses. Therefore, in general, addresses should be loaded by mov32. Change-Id: I9bcc3ee191f882996197ce2edc0eb510d4ff7b4a Reviewed-on: http://git-master/r/40460 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7ddd0d9b1e2fc8ab653b9220388acbecdbf4c57f
Diffstat (limited to 'arch/arm/mach-tegra/delay.S')
-rw-r--r--arch/arm/mach-tegra/delay.S4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/delay.S b/arch/arm/mach-tegra/delay.S
index 01123bfe6a0c..76bfafa76ebe 100644
--- a/arch/arm/mach-tegra/delay.S
+++ b/arch/arm/mach-tegra/delay.S
@@ -22,11 +22,13 @@
#include <mach/iomap.h>
#include <mach/io.h>
+#include "asm_macros.h"
+
.text
ENTRY(__udelay)
ENTRY(__const_udelay)
- ldr r3, =(IO_PPSB_VIRT + TEGRA_TMRUS_BASE - IO_PPSB_PHYS)
+ mov32 r3, (IO_PPSB_VIRT + TEGRA_TMRUS_BASE - IO_PPSB_PHYS)
ldr r1, [r3]
/* r0 - usecs to wait