diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-05-28 00:21:30 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:46 -0800 |
| commit | c86c2259fec1d947f16ca3a65085d481f320c4bb (patch) | |
| tree | f15315b66fad5b891d0a4549581464818d707450 /arch/arm/mach-tegra/devices.c | |
| parent | 3ea1f8b4b62acb995114da701ef2ebf420d02cd2 (diff) | |
ARM: tegra: clock: Change Tegra3 PLLP output frequency
On Tegra3 fixed PLLP output frequency has been set to 408MHz
(instead of 216MHz). Respectively changed:
- Tegra3 broads setting for UART, and audio clocks
- Tegra3 common clock setting for PLLP output dividers, SDMMC,
and system buses
- Tegra3 CPU backup configuration to guarantee safe backup at
any voltage
Bug 829081
Original-Change-Id: Ied0c75204ccb2e4a428f0b8a124f0f3e053aa386
Reviewed-on: http://git-master/r/34813
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rb9a445970ed83922394a24a732372c5541d8ef47
Diffstat (limited to 'arch/arm/mach-tegra/devices.c')
| -rw-r--r-- | arch/arm/mach-tegra/devices.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c index 1142a402b60d..39523ae61206 100644 --- a/arch/arm/mach-tegra/devices.c +++ b/arch/arm/mach-tegra/devices.c @@ -33,6 +33,12 @@ #include <mach/usb_phy.h> #include "gpio-names.h" +#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) +#define UART_SOURCE_RATE 408000000 +#else +#define UART_SOURCE_RATE 216000000 +#endif + static struct resource i2c_resource1[] = { [0] = { .start = INT_I2C, @@ -723,7 +729,7 @@ static struct plat_serial8250_port debug_uarta_platform_data[] = { .type = PORT_TEGRA, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = 216000000, + .uartclk = UART_SOURCE_RATE, }, { .flags = 0, @@ -739,7 +745,7 @@ static struct plat_serial8250_port debug_uartb_platform_data[] = { .type = PORT_TEGRA, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = 216000000, + .uartclk = UART_SOURCE_RATE, }, { .flags = 0, @@ -755,7 +761,7 @@ static struct plat_serial8250_port debug_uartc_platform_data[] = { .type = PORT_TEGRA, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = 216000000, + .uartclk = UART_SOURCE_RATE, }, { .flags = 0, @@ -771,7 +777,7 @@ static struct plat_serial8250_port debug_uartd_platform_data[] = { .type = PORT_TEGRA, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = 216000000, + .uartclk = UART_SOURCE_RATE, }, { .flags = 0, @@ -788,7 +794,7 @@ static struct plat_serial8250_port debug_uarte_platform_data[] = { .type = PORT_TEGRA, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = 216000000, + .uartclk = UART_SOURCE_RATE, }, { .flags = 0, |