Merge branch 'l4t/l4t-r16' into colibri

Merge with latest NVIDIA L4T R16.

Only real conflict concerning inverted VBUS gpio support.

1 files changed, 92 insertions, 41 deletions

diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 079d18e2339b..79f3ccc57f92 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -584,28 +584,6 @@ static struct resource tegra_usb3_resources[] = {
 	},
 };
 
-static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
-	/* All existing boards use GPIO PV0 for phy reset */
-	.reset_gpio = TEGRA_GPIO_PV0,
-	.clk = "cdev2",
-};
-
-static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
-	.operating_mode = TEGRA_USB_OTG,
-	.power_down_on_bus_suspend = 1,
-};
-
-static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
-	.phy_config = &tegra_ehci2_ulpi_phy_config,
-	.operating_mode = TEGRA_USB_HOST,
-	.power_down_on_bus_suspend = 1,
-};
-
-static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
-	.operating_mode = TEGRA_USB_HOST,
-	.power_down_on_bus_suspend = 1,
-};
-
 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
 
 struct platform_device tegra_ehci1_device = {
@@ -614,7 +592,6 @@ struct platform_device tegra_ehci1_device = {
 	.dev	= {
 		.dma_mask	= &tegra_ehci_dmamask,
 		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data = &tegra_ehci1_pdata,
 	},
 	.resource = tegra_usb1_resources,
 	.num_resources = ARRAY_SIZE(tegra_usb1_resources),
@@ -626,7 +603,6 @@ struct platform_device tegra_ehci2_device = {
 	.dev	= {
 		.dma_mask	= &tegra_ehci_dmamask,
 		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data = &tegra_ehci2_pdata,
 	},
 	.resource = tegra_usb2_resources,
 	.num_resources = ARRAY_SIZE(tegra_usb2_resources),
@@ -638,7 +614,6 @@ struct platform_device tegra_ehci3_device = {
 	.dev	= {
 		.dma_mask	= &tegra_ehci_dmamask,
 		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data = &tegra_ehci3_pdata,
 	},
 	.resource = tegra_usb3_resources,
 	.num_resources = ARRAY_SIZE(tegra_usb3_resources),
@@ -1216,6 +1191,11 @@ struct platform_device tegra_pcm_device = {
 	.id = -1,
 };
 
+struct platform_device tegra_tdm_pcm_device = {
+	.name = "tegra-tdm-pcm-audio",
+	.id = -1,
+};
+
 static struct resource w1_resources[] = {
 	[0] = {
 		.start = INT_OWR,
@@ -1251,18 +1231,12 @@ static struct resource tegra_udc_resources[] = {
 
 static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
 
-static struct fsl_usb2_platform_data tegra_udc_pdata = {
-	.operating_mode	= FSL_USB2_DR_DEVICE,
-	.phy_mode	= FSL_USB2_PHY_UTMI,
-};
-
 struct platform_device tegra_udc_device = {
-	.name	= "fsl-tegra-udc",
-	.id	= -1,
+	.name	= "tegra-udc",
+	.id	= 0,
 	.dev	= {
 		.dma_mask	= &tegra_udc_dmamask,
 		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data	= &tegra_udc_pdata,
 	},
 	.resource = tegra_udc_resources,
 	.num_resources = ARRAY_SIZE(tegra_udc_resources),
@@ -1424,16 +1398,23 @@ static struct resource tegra_wdt_resources[] = {
 		.flags	= IORESOURCE_IRQ,
 	},
 };
+
+struct platform_device tegra_wdt_device = {
+	.name		= "tegra_wdt",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(tegra_wdt_resources),
+	.resource	= tegra_wdt_resources,
+};
 #else
-static struct resource tegra_wdt_resources[] = {
+static struct resource tegra_wdt0_resources[] = {
 	[0] = {
 		.start	= TEGRA_WDT0_BASE,
 		.end	= TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= TEGRA_TMR10_BASE,
-		.end	= TEGRA_TMR10_BASE + TEGRA_TMR10_SIZE - 1,
+		.start	= TEGRA_TMR7_BASE,
+		.end	= TEGRA_TMR7_BASE + TEGRA_TMR7_SIZE - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	[2] = {
@@ -1441,16 +1422,64 @@ static struct resource tegra_wdt_resources[] = {
 		.end	= INT_WDT_CPU,
 		.flags	= IORESOURCE_IRQ,
 	},
-};
+#ifdef CONFIG_TEGRA_FIQ_DEBUGGER
+	[3] = {
+		.start	= TEGRA_QUATERNARY_ICTLR_BASE,
+		.end	= TEGRA_QUATERNARY_ICTLR_BASE + \
+				TEGRA_QUATERNARY_ICTLR_SIZE -1,
+		.flags	= IORESOURCE_MEM,
+	},
 #endif
+};
 
-struct platform_device tegra_wdt_device = {
+static struct resource tegra_wdt1_resources[] = {
+	[0] = {
+		.start	= TEGRA_WDT1_BASE,
+		.end	= TEGRA_WDT1_BASE + TEGRA_WDT1_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= TEGRA_TMR8_BASE,
+		.end	= TEGRA_TMR8_BASE + TEGRA_TMR8_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct resource tegra_wdt2_resources[] = {
+	[0] = {
+		.start	= TEGRA_WDT2_BASE,
+		.end	= TEGRA_WDT2_BASE + TEGRA_WDT2_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= TEGRA_TMR9_BASE,
+		.end	= TEGRA_TMR9_BASE + TEGRA_TMR9_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device tegra_wdt0_device = {
 	.name		= "tegra_wdt",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(tegra_wdt_resources),
-	.resource	= tegra_wdt_resources,
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(tegra_wdt0_resources),
+	.resource	= tegra_wdt0_resources,
+};
+
+struct platform_device tegra_wdt1_device = {
+	.name		= "tegra_wdt",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(tegra_wdt1_resources),
+	.resource	= tegra_wdt1_resources,
 };
 
+struct platform_device tegra_wdt2_device = {
+	.name		= "tegra_wdt",
+	.id		= 2,
+	.num_resources	= ARRAY_SIZE(tegra_wdt2_resources),
+	.resource	= tegra_wdt2_resources,
+};
+#endif
+
 static struct resource tegra_pwfm0_resource = {
 	.start	= TEGRA_PWFM0_BASE,
 	.end	= TEGRA_PWFM0_BASE + TEGRA_PWFM0_SIZE - 1,
@@ -1699,6 +1728,28 @@ struct platform_device tegra_nvmap_device = {
 	.id	= -1,
 };
 
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+static struct resource tegra_cec_resources[] = {
+	[0] = {
+		.start = TEGRA_CEC_BASE,
+		.end = TEGRA_CEC_BASE + TEGRA_CEC_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = INT_CEC,
+		.end = INT_CEC,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device tegra_cec_device = {
+	.name = "tegra_cec",
+	.id   = -1,
+	.resource = tegra_cec_resources,
+	.num_resources = ARRAY_SIZE(tegra_cec_resources),
+};
+#endif
+
 void __init tegra_init_debug_uart_rate(void)
 {
 	unsigned int uartclk;