diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-04-01 17:27:58 -0700 |
|---|---|---|
| committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2014-04-03 17:33:30 -0700 |
| commit | 928a2479e7e2018897377e7b63a9a6912894da7a (patch) | |
| tree | 8c71ad0bdc3b9696ea93a97e11e6d459c1fee6f7 /arch/arm/mach-tegra/dvfs.c | |
| parent | bfd498975e9750f52982faea7e64fdee19d1fe24 (diff) | |
ARM: tegra: clock: Use DFLL Vmin comparison interface
Used DFLL Vmin comparison interface to determine if CPU rail voltage
should be increased to account for temperature or SiMon grade change
before switching CPU cluster from LP to G.
Bug 1343366
Change-Id: I188cd8f7280a5b5361c59b244da6c8a4d729f05d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/391051
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/dvfs.c')
| -rw-r--r-- | arch/arm/mach-tegra/dvfs.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/dvfs.c b/arch/arm/mach-tegra/dvfs.c index e482bb203b90..7334deb35229 100644 --- a/arch/arm/mach-tegra/dvfs.c +++ b/arch/arm/mach-tegra/dvfs.c @@ -39,6 +39,7 @@ #include "board.h" #include "clock.h" #include "dvfs.h" +#include "tegra_cl_dvfs.h" #define DVFS_RAIL_STATS_BIN 12500 @@ -1995,7 +1996,8 @@ int __init tegra_dvfs_init_thermal_dvfs_voltages(int *therm_voltages, } /* Directly set cold temperature limit in dfll mode */ -int tegra_dvfs_rail_dfll_mode_set_cold(struct dvfs_rail *rail) +int tegra_dvfs_rail_dfll_mode_set_cold(struct dvfs_rail *rail, + struct clk *dfll_clk) { int ret = 0; @@ -2004,14 +2006,15 @@ int tegra_dvfs_rail_dfll_mode_set_cold(struct dvfs_rail *rail) return ret; /* - * Since cooling thresholds are the same in pll and dfll modes, pll mode - * thermal index can be used to decide if cold limit should be set in - * dfll mode. + * Compare last set Vmin with requirement based on current temperature, + * and set cold limit at regulator only Vmin is below requirement. */ mutex_lock(&dvfs_lock); if (rail->dfll_mode) { - int mv = tegra_dvfs_rail_get_thermal_floor(rail); - if (mv) + int mv, cmp; + cmp = tegra_cl_dvfs_vmin_cmp_needed( + tegra_dfll_get_cl_dvfs_data(dfll_clk), &mv); + if (cmp < 0) ret = dvfs_rail_set_voltage_reg(rail, mv); } mutex_unlock(&dvfs_lock); |