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authorAlex Frid <afrid@nvidia.com>2011-08-11 20:54:33 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:49:37 -0800
commit84cadce9be76a334bd3c6bf0c6f8e04d00657297 (patch)
tree6ae8bfeea920bba7007ad7fd071c9201008e2cd4 /arch/arm/mach-tegra/dvfs.h
parent2f8be47bd7c24f246b3573ee43dfcede03df1fe7 (diff)
ARM: tegra: power: Add Tegra3 balanced throttling
Balanced CPU and core domains thermal throttling on Tegra3. When throttling is enabled the new algorithm caps core bus frequencies (EMC, cbus and sbus) along with CPU rate. The throttling steps, and time spent on each step are pre-defined based on characterization results. (cherry picked from commit 0fa05e9904f369e201cad0c9be2b15e141d3624e) (cherry picked from commit 977e6bf94297347d8979b19877cf228325377d8f) Change-Id: I62bfcda7b5d6ba7b621e813f5d20ded7334a080f Reviewed-on: http://git-master/r/61024 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R0e65df5536ed7153a4a11dd299c5cd383b51c190
Diffstat (limited to 'arch/arm/mach-tegra/dvfs.h')
-rw-r--r--arch/arm/mach-tegra/dvfs.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h
index e5ddb63ba692..85077c005525 100644
--- a/arch/arm/mach-tegra/dvfs.h
+++ b/arch/arm/mach-tegra/dvfs.h
@@ -98,6 +98,8 @@ void tegra_dvfs_rail_enable(struct dvfs_rail *rail);
void tegra_dvfs_rail_disable(struct dvfs_rail *rail);
bool tegra_dvfs_rail_updating(struct clk *clk);
int tegra_dvfs_predict_millivolts(struct clk *c, unsigned long rate);
+void tegra_dvfs_core_cap_enable(bool enable);
+void tegra_dvfs_core_cap_level_set(int level);
#else
static inline void tegra_soc_init_dvfs(void)
{}
@@ -119,6 +121,10 @@ static inline bool tegra_dvfs_rail_updating(struct clk *clk)
{ return false; }
static inline int tegra_dvfs_predict_millivolts(struct clk *c, unsigned long rate)
{ return 0; }
+static inline void tegra_dvfs_core_cap_enable(bool enable)
+{}
+static inline void tegra_dvfs_core_cap_level_set(int level)
+{}
#endif
#endif