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authorAntti P Miettinen <amiettinen@nvidia.com>2012-12-07 23:32:42 +0200
committerDan Willemsen <dwillemsen@nvidia.com>2013-09-14 12:48:20 -0700
commit52088ff2a6b6869d9220c5b86b04465dbc8df068 (patch)
tree7b4c37acd51910cde8464b29bb3323f216cead22 /arch/arm/mach-tegra/flowctrl.c
parentdf2f4561b463318714f7de5a84ce178e76dad23b (diff)
ARM: Tegra: Use relaxed register access
No need to include heavy barriers for register access. Change-Id: I55c664e196ec02a352b705a528882797169a1309 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/169492 Reviewed-by: Harshada Kale <hkale@nvidia.com> Tested-by: Harshada Kale <hkale@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/flowctrl.c')
-rw-r--r--arch/arm/mach-tegra/flowctrl.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index ffaa286a71e1..cb17e207a59e 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -43,7 +43,7 @@ static void flowctrl_update(u8 offset, u32 value)
{
void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
- writel(value, addr);
+ writel_relaxed(value, addr);
/* ensure the update has reached the flow controller */
wmb();