diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-02-02 10:32:42 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:51:40 -0700 |
| commit | 7df947103b10608106d2b10fbc951af68926438e (patch) | |
| tree | 0d9e914ae54859f4ebb590a26b91d74adcadbf64 /arch/arm/mach-tegra/headsmp-t3.S | |
| parent | 4c609cbf4d1f0cf1a3f78c72695e3168b6088a4a (diff) | |
arm: tegra: Redesign Tegra CPU reset handling
- Add a single unified handler for all CPU resets.
- Don't write boot confirmation notification to the reset vector.
- Write the EVP CPU reset vector only once per cold/warm boot session.
- Don't allow Tegra3 LP2 until all CPUs have booted.
- Don't restart online secondary CPUs that are also in LP2 state
when restarting CPU0 for Tegra3.
- Prevent the compiler from rearranging order-sensitive register
writes in boot_secondary().
- Fix incorrect return status in tegra_powergate_is_powered().
- In LP2 entry code, if a WFI request fails, retry a limited number
of times.
- Eliminate duplicate macro definitions.
- Improve commentary in assembly functions.
Bug 786290
Bug 790458
Original-Change-Id: I7582112938aa80303d1b8b1d1948d278ca662043
Reviewed-on: http://git-master/r/18091
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I56a686e2e9fc00e61e97eec4fbf5a49944ffa77c
Diffstat (limited to 'arch/arm/mach-tegra/headsmp-t3.S')
| -rw-r--r-- | arch/arm/mach-tegra/headsmp-t3.S | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/arch/arm/mach-tegra/headsmp-t3.S b/arch/arm/mach-tegra/headsmp-t3.S index 5554f3634aee..f656e41f37a3 100644 --- a/arch/arm/mach-tegra/headsmp-t3.S +++ b/arch/arm/mach-tegra/headsmp-t3.S @@ -31,6 +31,7 @@ #include <mach/iomap.h> #include <mach/io.h> +#include "power.h" #include "power-macros.S" #define TTB_FLAGS 0x6A @ IRGN_WBWA, OC_RGN_WBWA, S, NOS @@ -97,9 +98,6 @@ ENDPROC(__restart_plls) */ .align L1_CACHE_SHIFT ENTRY(tegra_lp2_startup) -#if DEBUG_LP2_STARTUP - b . -#endif setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 mov32 r0, TEGRA_TMRUS_BASE @@ -113,19 +111,21 @@ ENTRY(tegra_lp2_startup) bl __invalidate_cpu_state bl __enable_coresite_access -#ifdef DEBUG - cpu_id r0 - cmp r0, #0 - bne . @ should only come here for CPU0 +#if DEBUG_LP2_STARTUP + b . #endif - @ Clear the flow controller flags for this CPU. - mov32 r2, TEGRA_FLOW_CTRL_BASE+8 @ CPU0 CSR - ldr r1, [r2] + cpu_id r0 + subs r0, r0, #1 + movmi r2, #FLOW_CTLR_CPU_CSR @ CPU0 CSR + movpl r2, r0, lsl #8 + addpl r2, r2, #FLOW_CTLR_CPU1_CSR @ CPUn CSR, n == 1,2,3 + mov32 r4, TEGRA_FLOW_CTRL_BASE + ldr r1, [r4, +r2] orr r1, r1, #(1 << 15) | (1 << 14) @ write to clear event & intr movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps bic r1, r1, r0 - str r1, [r2] + str r1, [r4, +r2] mrc p15, 0, r0, c1, c0, 1 orr r0, r0, #(1 << 6) | (1 << 0) @ re-enable coherency @@ -171,7 +171,6 @@ ENTRY(tegra_hotplug_startup) cpu_id r0 subs r1, r0, #1 #ifdef DEBUG - /* !!!CHECKME!!! THIS MAY NOW BE OBSOLETE */ bmi . @ should never come here for CPU0 #endif mov r3, r1, lsl #3 |