diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-06-29 11:45:53 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:49 -0800 |
| commit | f944d3f344ca055c0bbba80010ca2b6786c27bb3 (patch) | |
| tree | c3eb29d3e11ef7f6c3722c3f2e9139b2c6221671 /arch/arm/mach-tegra/headsmp.S | |
| parent | 150a0bd861b0032f0272d982a00b2e980b94d417 (diff) | |
ARM: tegra: power: Prefer movw/movt for loading addresses
The movw/movt instruction pair (encapsulated by the mov32 macro)
is preferred over literals for loading addresses. The use of literals
for singleton data accesses can cause unnecessary cache misses and
evictions for cache lines that are unlikely to be accessed again in
the near future. Furthermore, certain code sequences must refrain
from using data accesses. Therefore, in general, addresses should
be loaded by mov32.
Change-Id: I9bcc3ee191f882996197ce2edc0eb510d4ff7b4a
Reviewed-on: http://git-master/r/40460
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R7ddd0d9b1e2fc8ab653b9220388acbecdbf4c57f
Diffstat (limited to 'arch/arm/mach-tegra/headsmp.S')
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index e746423b543b..73d270c51bdd 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -27,6 +27,8 @@ #include <mach/iomap.h> +#include "asm_macros.h" + #ifdef CONFIG_SMP /* * tegra_secondary_startup @@ -79,7 +81,7 @@ ENTRY(tegra_resume) #endif /* enable SCU */ - ldr r0, =TEGRA_ARM_PERIF_BASE + mov32 r0, TEGRA_ARM_PERIF_BASE ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -129,6 +131,6 @@ tegra_invalidate_l1: /* Enable Coresight access on cpu */ tegra_enable_coresite: - ldr r0, =0xC5ACCE55 + mov32 r0, 0xC5ACCE55 mcr p14, 0, r0, c7, c12, 6 mov pc, lr |