diff options
| author | Vandana Salve <vsalve@nvidia.com> | 2012-03-13 14:11:41 +0530 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-07-11 06:36:38 -0700 |
| commit | 22b1ce014b037ed8e48fa15eb144c783f18659ed (patch) | |
| tree | 665ceeb625e2590dcc83d782fc2a1805dc991b5b /arch/arm/mach-tegra/include/mach | |
| parent | 679f252f2320851d7d7fae4535a883de0cf1cdb4 (diff) | |
ARM: tegra: iomap: Introduce TEGRA_IOMMU_{BASE,SIZE} for SMMU/GART
Replace TEGRA_{SMMU,GART}_{BASE,SIZE} with TEGRA_IOMMU_{BASE,SIZE} to
deal with SMMU/GART in unified manner.
This is necessary for DMA mapping API to pass the appropriate IOMMU
address for SMMU and GART in the same code in nvmap.
[Hiroshi Doyu: Squash nvmap parts into "nvmap: API conversion" patch.]
Change-Id: I75429dd56554f880f144c375d2c20e8e8948ceee
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/114212
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/include/mach')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/iomap.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index 6d3a1aff0cfe..2e205db063dd 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -2,7 +2,7 @@ * arch/arm/mach-tegra/include/mach/iomap.h * * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2011 NVIDIA Corporation. + * Copyright (C) 2011-2012, NVIDIA Corporation. * * Author: * Colin Cross <ccross@google.com> @@ -92,6 +92,8 @@ #define TEGRA_GART_BASE 0x58000000 #define TEGRA_GART_SIZE SZ_32M +#define TEGRA_IOMMU_BASE TEGRA_GART_BASE +#define TEGRA_IOMMU_SIZE TEGRA_GART_SIZE #else @@ -99,6 +101,8 @@ #define TEGRA_SMMU_SIZE_TEGRA3_A01 SZ_256M #define TEGRA_SMMU_BASE 0x00001000 #define TEGRA_SMMU_SIZE (SZ_1G - SZ_4K * 2) +#define TEGRA_IOMMU_BASE TEGRA_SMMU_BASE +#define TEGRA_IOMMU_SIZE TEGRA_SMMU_SIZE #endif |