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authorStefan Agner <stefan.agner@toradex.com>2014-01-28 17:37:08 +0100
committerStefan Agner <stefan.agner@toradex.com>2014-01-29 15:12:46 +0100
commit0a4e373dc430abd981b15d392098c9e32a134acd (patch)
treede35375d1cd444274e976b6ebfbbabb1c164c500 /arch/arm/mach-tegra/include
parent8a87a46328d2e248cf11e1d2588ef42d67110b73 (diff)
video: tegra: kernel parameters to change RGB clock polarity
Allow to change clock polarity for RGB display output using the keywords outputen/pixclockpol/vsync and hsync. Add them right after the driver specification, use 0/1 to specifiy high/low polarity, e.g. video=tegrafb0:pixclockpol:1,800x480
Diffstat (limited to 'arch/arm/mach-tegra/include')
-rw-r--r--arch/arm/mach-tegra/include/mach/dc.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h
index 13dc8c0be03a..a60e3e5b14fa 100644
--- a/arch/arm/mach-tegra/include/mach/dc.h
+++ b/arch/arm/mach-tegra/include/mach/dc.h
@@ -353,7 +353,7 @@ struct tegra_dc_out {
unsigned depth;
unsigned dither;
- const char *default_mode;
+ char *default_mode;
struct tegra_dc_mode *modes;
int n_modes;