diff options
| author | Krishna Reddy <vdumpa@nvidia.com> | 2012-08-13 12:37:32 -0700 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-08-15 17:12:57 -0700 |
| commit | 361f7676aaecfd0157b89f0e106f59fcc229a839 (patch) | |
| tree | f66e0c369bacdea5bc789dc9a77da9b42485cb2e /arch/arm/mach-tegra/include | |
| parent | 028042d5cc554c41a7b5f00fc2b20dce997fcc43 (diff) | |
arm: tegra: la: refactor la code.
This is necessary to support future tegra SOC's.
Change-Id: I2f6ce328e30a6895dce16d82c4097291339155cd
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/123146
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'arch/arm/mach-tegra/include')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/latency_allowance.h | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/arch/arm/mach-tegra/include/mach/latency_allowance.h b/arch/arm/mach-tegra/include/mach/latency_allowance.h index 8644075a88b3..5ebc6f03b810 100644 --- a/arch/arm/mach-tegra/include/mach/latency_allowance.h +++ b/arch/arm/mach-tegra/include/mach/latency_allowance.h @@ -18,19 +18,19 @@ #define _MACH_TEGRA_LATENCY_ALLOWANCE_H_ enum tegra_la_id { - TEGRA_LA_AFIR = 0, - TEGRA_LA_AFIW, + TEGRA_LA_AFIR = 0, /* T30 specific */ + TEGRA_LA_AFIW, /* T30 specific */ TEGRA_LA_AVPC_ARM7R, TEGRA_LA_AVPC_ARM7W, TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B, TEGRA_LA_DISPLAY_0C, - TEGRA_LA_DISPLAY_1B, + TEGRA_LA_DISPLAY_1B, /* T30 specific */ TEGRA_LA_DISPLAY_HC, TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB, TEGRA_LA_DISPLAY_0CB, - TEGRA_LA_DISPLAY_1BB, + TEGRA_LA_DISPLAY_1BB, /* T30 specific */ TEGRA_LA_DISPLAY_HCB, TEGRA_LA_EPPUP, TEGRA_LA_EPPU, @@ -50,27 +50,27 @@ enum tegra_la_id { TEGRA_LA_MPCOREW, TEGRA_LA_MPCORE_LPR, TEGRA_LA_MPCORE_LPW, - TEGRA_LA_MPE_UNIFBR, - TEGRA_LA_MPE_IPRED, - TEGRA_LA_MPE_AMEMRD, - TEGRA_LA_MPE_CSRD, - TEGRA_LA_MPE_UNIFBW, - TEGRA_LA_MPE_CSWR, + TEGRA_LA_MPE_UNIFBR, /* T30 specific */ + TEGRA_LA_MPE_IPRED, /* T30 specific */ + TEGRA_LA_MPE_AMEMRD, /* T30 specific */ + TEGRA_LA_MPE_CSRD, /* T30 specific */ + TEGRA_LA_MPE_UNIFBW, /* T30 specific */ + TEGRA_LA_MPE_CSWR, /* T30 specific */ TEGRA_LA_FDCDRD, TEGRA_LA_IDXSRD, TEGRA_LA_TEXSRD, TEGRA_LA_FDCDWR, TEGRA_LA_FDCDRD2, - TEGRA_LA_IDXSRD2, - TEGRA_LA_TEXSRD2, + TEGRA_LA_IDXSRD2, /* T30 specific */ + TEGRA_LA_TEXSRD2, /* T30 specific */ TEGRA_LA_FDCDWR2, TEGRA_LA_PPCS_AHBDMAR, TEGRA_LA_PPCS_AHBSLVR, TEGRA_LA_PPCS_AHBDMAW, TEGRA_LA_PPCS_AHBSLVW, TEGRA_LA_PTCR, - TEGRA_LA_SATAR, - TEGRA_LA_SATAW, + TEGRA_LA_SATAR, /* T30 specific */ + TEGRA_LA_SATAW, /* T30 specific */ TEGRA_LA_VDE_BSEVR, TEGRA_LA_VDE_MBER, TEGRA_LA_VDE_MCER, @@ -79,11 +79,12 @@ enum tegra_la_id { TEGRA_LA_VDE_DBGW, TEGRA_LA_VDE_MBEW, TEGRA_LA_VDE_TPMW, - TEGRA_LA_VI_RUV, + TEGRA_LA_VI_RUV, /* T30 specific */ TEGRA_LA_VI_WSB, TEGRA_LA_VI_WU, TEGRA_LA_VI_WV, TEGRA_LA_VI_WY, + TEGRA_LA_MAX_ID }; |