diff options
| author | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-13 15:43:11 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:55:31 -0700 |
| commit | 679662e71e29c7ec9c56ca64268d5d53eb740ff5 (patch) | |
| tree | d90d9fbeae471e39003d2346b5ae76ce98fbeedb /arch/arm/mach-tegra/include | |
| parent | a7331778a4a1acb159f9f984df141a6832aab1c0 (diff) | |
ARM: tegra: Reformat tegra2_i2s.h
Change-Id: Ibf2914683b617ef036c7c9abc89ed9407a2d2a07
Diffstat (limited to 'arch/arm/mach-tegra/include')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/tegra2_i2s.h | 89 |
1 files changed, 55 insertions, 34 deletions
diff --git a/arch/arm/mach-tegra/include/mach/tegra2_i2s.h b/arch/arm/mach-tegra/include/mach/tegra2_i2s.h index f37b96cc04be..46328c5d166d 100644 --- a/arch/arm/mach-tegra/include/mach/tegra2_i2s.h +++ b/arch/arm/mach-tegra/include/mach/tegra2_i2s.h @@ -49,7 +49,7 @@ #define I2S_I2S_CTRL_FIFO1_RX_ENABLE (1<<27) #define I2S_I2S_CTRL_FIFO_LPBK_ENABLE (1<<26) #define I2S_I2S_CTRL_MASTER_ENABLE (1<<25) -#define I2S_I2S_CTRL_L_R_CTRL (1<<24) /* 0 = Left low/Right high */ +#define I2S_I2S_CTRL_L_R_CTRL (1<<24) #define I2S_BIT_FORMAT_I2S 0 #define I2S_BIT_FORMAT_RJM 1 @@ -69,11 +69,16 @@ #define I2S_BIT_SIZE_32 3 #define I2S_BIT_SIZE_SHIFT 8 -#define I2S_I2S_CTRL_BIT_SIZE_MASK (3 << I2S_BIT_SIZE_SHIFT) -#define I2S_I2S_CTRL_BIT_SIZE_16 (I2S_BIT_SIZE_16 << I2S_BIT_SIZE_SHIFT) -#define I2S_I2S_CTRL_BIT_SIZE_20 (I2S_BIT_SIZE_20 << I2S_BIT_SIZE_SHIFT) -#define I2S_I2S_CTRL_BIT_SIZE_24 (I2S_BIT_SIZE_24 << I2S_BIT_SIZE_SHIFT) -#define I2S_I2S_CTRL_BIT_SIZE_32 (I2S_BIT_SIZE_32 << I2S_BIT_SIZE_SHIFT) +#define I2S_I2S_CTRL_BIT_SIZE_MASK \ + (3 << I2S_BIT_SIZE_SHIFT) +#define I2S_I2S_CTRL_BIT_SIZE_16 \ + (I2S_BIT_SIZE_16 << I2S_BIT_SIZE_SHIFT) +#define I2S_I2S_CTRL_BIT_SIZE_20 \ + (I2S_BIT_SIZE_20 << I2S_BIT_SIZE_SHIFT) +#define I2S_I2S_CTRL_BIT_SIZE_24 \ + (I2S_BIT_SIZE_24 << I2S_BIT_SIZE_SHIFT) +#define I2S_I2S_CTRL_BIT_SIZE_32 \ + (I2S_BIT_SIZE_32 << I2S_BIT_SIZE_SHIFT) #define I2S_FIFO_16_LSB 0 #define I2S_FIFO_20_LSB 1 @@ -83,21 +88,27 @@ #define I2S_FIFO_SHIFT 4 #define I2S_I2S_CTRL_FIFO_FORMAT_MASK (7<<4) -#define I2S_I2S_CTRL_FIFO_FORMAT_16_LSB (I2S_FIFO_16_LSB << I2S_FIFO_SHIFT) -#define I2S_I2S_CTRL_FIFO_FORMAT_20_LSB (I2S_FIFO_20_LSB << I2S_FIFO_SHIFT) -#define I2S_I2S_CTRL_FIFO_FORMAT_24_LSB (I2S_FIFO_24_LSB << I2S_FIFO_SHIFT) -#define I2S_I2S_CTRL_FIFO_FORMAT_32 (I2S_FIFO_32 << I2S_FIFO_SHIFT) -#define I2S_I2S_CTRL_FIFO_FORMAT_PACKED (I2S_FIFO_PACKED << I2S_FIFO_SHIFT) +#define I2S_I2S_CTRL_FIFO_FORMAT_16_LSB \ + (I2S_FIFO_16_LSB << I2S_FIFO_SHIFT) +#define I2S_I2S_CTRL_FIFO_FORMAT_20_LSB \ + (I2S_FIFO_20_LSB << I2S_FIFO_SHIFT) +#define I2S_I2S_CTRL_FIFO_FORMAT_24_LSB \ + (I2S_FIFO_24_LSB << I2S_FIFO_SHIFT) +#define I2S_I2S_CTRL_FIFO_FORMAT_32 \ + (I2S_FIFO_32 << I2S_FIFO_SHIFT) +#define I2S_I2S_CTRL_FIFO_FORMAT_PACKED \ + (I2S_FIFO_PACKED << I2S_FIFO_SHIFT) -// Left/Right Control Polarity. 0= Left channel when LRCK is low, Right channel when LRCK is high, 1= vice versa -#define I2S_LRCK_LEFT_LOW 0 -#define I2S_LRCK_RIGHT_LOW 1 -#define I2S_LRCK_SHIFT 24 +// Left/Right Control Polarity. 0= Left channel when LRCK is low, +// Right channel when LRCK is high, 1= vice versa +#define I2S_LRCK_LEFT_LOW 0 +#define I2S_LRCK_RIGHT_LOW 1 +#define I2S_LRCK_SHIFT 24 -#define I2S_I2S_CTRL_LRCK_MASK (1<<I2S_LRCK_SHIFT) -#define I2S_I2S_CTRL_LRCK_L_LOW (I2S_LRCK_LEFT_LOW << I2S_LRCK_SHIFT) -#define I2S_I2S_CTRL_LRCK_R_LOW (I2S_LRCK_RIGHT_LOW << I2S_LRCK_SHIFT) +#define I2S_I2S_CTRL_LRCK_MASK (1<<I2S_LRCK_SHIFT) +#define I2S_I2S_CTRL_LRCK_L_LOW (I2S_LRCK_LEFT_LOW << I2S_LRCK_SHIFT) +#define I2S_I2S_CTRL_LRCK_R_LOW (I2S_LRCK_RIGHT_LOW << I2S_LRCK_SHIFT) #define I2S_I2S_IE_FIFO1_ERR (1<<3) @@ -130,15 +141,15 @@ * I2S_I2S_FIFO_SCR_0 */ -#define I2S_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK 0x3f -#define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24 -#define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16 +#define I2S_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK 0x3f +#define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24 +#define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16 #define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_MASK (0x3f<<24) #define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_MASK (0x3f<<16) -#define I2S_I2S_FIFO_SCR_FIFO2_CLR (1<<12) -#define I2S_I2S_FIFO_SCR_FIFO1_CLR (1<<8) +#define I2S_I2S_FIFO_SCR_FIFO2_CLR (1<<12) +#define I2S_I2S_FIFO_SCR_FIFO1_CLR (1<<8) #define I2S_FIFO_ATN_LVL_ONE_SLOT 0 #define I2S_FIFO_ATN_LVL_FOUR_SLOTS 1 @@ -147,17 +158,27 @@ #define I2S_FIFO2_ATN_LVL_SHIFT 4 #define I2S_FIFO1_ATN_LVL_SHIFT 0 -#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK (3 << I2S_FIFO2_ATN_LVL_SHIFT) -#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT (I2S_FIFO_ATN_LVL_ONE_SLOT << I2S_FIFO2_ATN_LVL_SHIFT) -#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS (I2S_FIFO_ATN_LVL_FOUR_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT) -#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS (I2S_FIFO_ATN_LVL_EIGHT_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT) -#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT) - -#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK (3 << I2S_FIFO1_ATN_LVL_SHIFT) -#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT (I2S_FIFO_ATN_LVL_ONE_SLOT << I2S_FIFO1_ATN_LVL_SHIFT) -#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS (I2S_FIFO_ATN_LVL_FOUR_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT) -#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS (I2S_FIFO_ATN_LVL_EIGHT_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT) -#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT) +#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK \ + (3 << I2S_FIFO2_ATN_LVL_SHIFT) +#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT \ + (I2S_FIFO_ATN_LVL_ONE_SLOT << I2S_FIFO2_ATN_LVL_SHIFT) +#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS \ + (I2S_FIFO_ATN_LVL_FOUR_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT) +#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS \ + (I2S_FIFO_ATN_LVL_EIGHT_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT) +#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS \ + (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT) + +#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK \ + (3 << I2S_FIFO1_ATN_LVL_SHIFT) +#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT \ + (I2S_FIFO_ATN_LVL_ONE_SLOT << I2S_FIFO1_ATN_LVL_SHIFT) +#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS \ + (I2S_FIFO_ATN_LVL_FOUR_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT) +#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS \ + (I2S_FIFO_ATN_LVL_EIGHT_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT) +#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS \ + (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT) /* * I2S_I2S_PCM_CTRL_0 |