diff options
| author | Gary King <gking@nvidia.com> | 2010-05-23 22:17:48 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-05-23 22:17:48 -0700 |
| commit | bda1dbe0ed94ba4f4f8e22a4362a5169555ba22b (patch) | |
| tree | 742de4de1e093a05e0cb4c3c572b4efad27619d2 /arch/arm/mach-tegra/include | |
| parent | a3139a93eeb76430edbfd1d39675366bc1a693aa (diff) | |
[ARM/tegra] add PCI driver
Change-Id: I89e73a9247d48ddb808065f0f697b9fabcfc2901
Diffstat (limited to 'arch/arm/mach-tegra/include')
| -rw-r--r-- | arch/arm/mach-tegra/include/ap20/arafi.h | 2914 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/ap20/dev_ap_pcie2_pads.h | 466 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/ap20/dev_ap_pcie2_root_port.h | 2085 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/hardware.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/iomap.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/pci.h | 337 |
6 files changed, 5809 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/ap20/arafi.h b/arch/arm/mach-tegra/include/ap20/arafi.h new file mode 100644 index 000000000000..1be73682f4fe --- /dev/null +++ b/arch/arm/mach-tegra/include/ap20/arafi.h @@ -0,0 +1,2914 @@ +/* + * Copyright (c) 2009 NVIDIA Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the NVIDIA Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ +// +// DO NOT EDIT - generated by simspec! +// + +#ifndef ___ARAFI_H_INC_ +#define ___ARAFI_H_INC_ + +// Register AFI_AXI_BAR0_SZ_0 +#define AFI_AXI_BAR0_SZ_0 _MK_ADDR_CONST(0x0) +#define AFI_AXI_BAR0_SZ_0_SECURE 0x0 +#define AFI_AXI_BAR0_SZ_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR0_SZ_0_RESET_VAL _MK_MASK_CONST(0x40000) +#define AFI_AXI_BAR0_SZ_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR0_SZ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR0_SZ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR0_SZ_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR0_SZ_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +//The size of the address range associated with BARi is in 4K increments. +//Value of 0 signifies BARi is not used. +#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_SHIFT) +#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_RANGE 19:0 +#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_WOFFSET 0x0 +#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_DEFAULT _MK_MASK_CONST(0x40000) +#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR1_SZ_0 +#define AFI_AXI_BAR1_SZ_0 _MK_ADDR_CONST(0x4) +#define AFI_AXI_BAR1_SZ_0_SECURE 0x0 +#define AFI_AXI_BAR1_SZ_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR1_SZ_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR1_SZ_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR1_SZ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR1_SZ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR1_SZ_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR1_SZ_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +//The size of the address range associated with BARi is in 4K increments. +//Value of 0 signifies BARi is not used. +#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_SHIFT) +#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_RANGE 19:0 +#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_WOFFSET 0x0 +#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR2_SZ_0 +#define AFI_AXI_BAR2_SZ_0 _MK_ADDR_CONST(0x8) +#define AFI_AXI_BAR2_SZ_0_SECURE 0x0 +#define AFI_AXI_BAR2_SZ_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR2_SZ_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR2_SZ_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR2_SZ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR2_SZ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR2_SZ_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR2_SZ_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +//The size of the address range associated with BARi is in 4K increments. +//Value of 0 signifies BARi is not used. +#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_SHIFT) +#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_RANGE 19:0 +#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_WOFFSET 0x0 +#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR3_SZ_0 +#define AFI_AXI_BAR3_SZ_0 _MK_ADDR_CONST(0xc) +#define AFI_AXI_BAR3_SZ_0_SECURE 0x0 +#define AFI_AXI_BAR3_SZ_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR3_SZ_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR3_SZ_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR3_SZ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR3_SZ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR3_SZ_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR3_SZ_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +//The size of the address range associated with BARi is in 4K increments. +//Value of 0 signifies BARi is not used. +#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_SHIFT) +#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_RANGE 19:0 +#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_WOFFSET 0x0 +#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR4_SZ_0 +#define AFI_AXI_BAR4_SZ_0 _MK_ADDR_CONST(0x10) +#define AFI_AXI_BAR4_SZ_0_SECURE 0x0 +#define AFI_AXI_BAR4_SZ_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR4_SZ_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR4_SZ_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR4_SZ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR4_SZ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR4_SZ_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR4_SZ_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +//The size of the address range associated with BARi is in 4K increments. +//Value of 0 signifies BARi is not used. +#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_SHIFT) +#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_RANGE 19:0 +#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_WOFFSET 0x0 +#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR5_SZ_0 +#define AFI_AXI_BAR5_SZ_0 _MK_ADDR_CONST(0x14) +#define AFI_AXI_BAR5_SZ_0_SECURE 0x0 +#define AFI_AXI_BAR5_SZ_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR5_SZ_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR5_SZ_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR5_SZ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR5_SZ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR5_SZ_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR5_SZ_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +//The size of the address range associated with BARi is in 4K increments. +//Value of 0 signifies BARi is not used. +#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_SHIFT) +#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_RANGE 19:0 +#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_WOFFSET 0x0 +#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR0_START_0 +#define AFI_AXI_BAR0_START_0 _MK_ADDR_CONST(0x18) +#define AFI_AXI_BAR0_START_0_SECURE 0x0 +#define AFI_AXI_BAR0_START_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR0_START_0_RESET_VAL _MK_MASK_CONST(0x80000000) +#define AFI_AXI_BAR0_START_0_RESET_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR0_START_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR0_START_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR0_START_0_READ_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR0_START_0_WRITE_MASK _MK_MASK_CONST(0xfffff000) +//The start of AXI address space for BARi. +//The AXI target address is compared to start/size for each BAR +//to determine if the access is to that BAR. +#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_SHIFT _MK_SHIFT_CONST(12) +#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR0_START_0_AXI_BAR0_START_SHIFT) +#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_RANGE 31:12 +#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_WOFFSET 0x0 +#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_DEFAULT _MK_MASK_CONST(0x80000) +#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR1_START_0 +#define AFI_AXI_BAR1_START_0 _MK_ADDR_CONST(0x1c) +#define AFI_AXI_BAR1_START_0_SECURE 0x0 +#define AFI_AXI_BAR1_START_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR1_START_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR1_START_0_RESET_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR1_START_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR1_START_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR1_START_0_READ_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR1_START_0_WRITE_MASK _MK_MASK_CONST(0xfffff000) +//The start of AXI address space for BARi. +//The AXI target address is compared to start/size for each BAR +//to determine if the access is to that BAR. +#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_SHIFT _MK_SHIFT_CONST(12) +#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR1_START_0_AXI_BAR1_START_SHIFT) +#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_RANGE 31:12 +#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_WOFFSET 0x0 +#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR2_START_0 +#define AFI_AXI_BAR2_START_0 _MK_ADDR_CONST(0x20) +#define AFI_AXI_BAR2_START_0_SECURE 0x0 +#define AFI_AXI_BAR2_START_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR2_START_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR2_START_0_RESET_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR2_START_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR2_START_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR2_START_0_READ_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR2_START_0_WRITE_MASK _MK_MASK_CONST(0xfffff000) +//The start of AXI address space for BARi. +//The AXI target address is compared to start/size for each BAR +//to determine if the access is to that BAR. +#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_SHIFT _MK_SHIFT_CONST(12) +#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR2_START_0_AXI_BAR2_START_SHIFT) +#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_RANGE 31:12 +#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_WOFFSET 0x0 +#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR3_START_0 +#define AFI_AXI_BAR3_START_0 _MK_ADDR_CONST(0x24) +#define AFI_AXI_BAR3_START_0_SECURE 0x0 +#define AFI_AXI_BAR3_START_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR3_START_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR3_START_0_RESET_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR3_START_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR3_START_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR3_START_0_READ_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR3_START_0_WRITE_MASK _MK_MASK_CONST(0xfffff000) +//The start of AXI address space for BARi. +//The AXI target address is compared to start/size for each BAR +//to determine if the access is to that BAR. +#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_SHIFT _MK_SHIFT_CONST(12) +#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR3_START_0_AXI_BAR3_START_SHIFT) +#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_RANGE 31:12 +#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_WOFFSET 0x0 +#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR4_START_0 +#define AFI_AXI_BAR4_START_0 _MK_ADDR_CONST(0x28) +#define AFI_AXI_BAR4_START_0_SECURE 0x0 +#define AFI_AXI_BAR4_START_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR4_START_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR4_START_0_RESET_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR4_START_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR4_START_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR4_START_0_READ_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR4_START_0_WRITE_MASK _MK_MASK_CONST(0xfffff000) +//The start of AXI address space for BARi. +//The AXI target address is compared to start/size for each BAR +//to determine if the access is to that BAR. +#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_SHIFT _MK_SHIFT_CONST(12) +#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR4_START_0_AXI_BAR4_START_SHIFT) +#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_RANGE 31:12 +#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_WOFFSET 0x0 +#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AXI_BAR5_START_0 +#define AFI_AXI_BAR5_START_0 _MK_ADDR_CONST(0x2c) +#define AFI_AXI_BAR5_START_0_SECURE 0x0 +#define AFI_AXI_BAR5_START_0_WORD_COUNT 0x1 +#define AFI_AXI_BAR5_START_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR5_START_0_RESET_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR5_START_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR5_START_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR5_START_0_READ_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_AXI_BAR5_START_0_WRITE_MASK _MK_MASK_CONST(0xfffff000) +//The start of AXI address space for BARi. +//The AXI target address is compared to start/size for each BAR +//to determine if the access is to that BAR. +#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_SHIFT _MK_SHIFT_CONST(12) +#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_FIELD (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR5_START_0_AXI_BAR5_START_SHIFT) +#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_RANGE 31:12 +#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_WOFFSET 0x0 +#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_FPCI_BAR0_0 +#define AFI_FPCI_BAR0_0 _MK_ADDR_CONST(0x30) +#define AFI_FPCI_BAR0_0_SECURE 0x0 +#define AFI_FPCI_BAR0_0_WORD_COUNT 0x1 +#define AFI_FPCI_BAR0_0_RESET_VAL _MK_MASK_CONST(0x800001) +#define AFI_FPCI_BAR0_0_RESET_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR0_0_READ_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR0_0_WRITE_MASK _MK_MASK_CONST(0xfffffff1) +//The start of FPCI address space mapped into the BARi +//range of PCI memory space. The 40-bit FPCI address is determined +//by a a shift left 8 of the value of this register. +#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_SHIFT _MK_SHIFT_CONST(4) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_FIELD (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR0_0_FPCI_BAR0_START_SHIFT) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_RANGE 31:4 +#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_WOFFSET 0x0 +#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_DEFAULT _MK_MASK_CONST(0x80000) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_DEFAULT_MASK _MK_MASK_CONST(0xfffffff) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Indicates if the address region is memory +//mapped versus configuration or IO space. +//1=memory mapped access (PW only) +//0=IO/config access (NWP only) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_FIELD (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_SHIFT) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_RANGE 0:0 +#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_WOFFSET 0x0 +#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_FPCI_BAR1_0 +#define AFI_FPCI_BAR1_0 _MK_ADDR_CONST(0x34) +#define AFI_FPCI_BAR1_0_SECURE 0x0 +#define AFI_FPCI_BAR1_0_WORD_COUNT 0x1 +#define AFI_FPCI_BAR1_0_RESET_VAL _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR1_0_RESET_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR1_0_READ_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR1_0_WRITE_MASK _MK_MASK_CONST(0xfffffff1) +//The start of FPCI address space mapped into the BARi +//range of PCI memory space. The 40-bit FPCI address is determined +//by a a shift left 8 of the value of this register. +#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_SHIFT _MK_SHIFT_CONST(4) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_FIELD (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR1_0_FPCI_BAR1_START_SHIFT) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_RANGE 31:4 +#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_WOFFSET 0x0 +#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_DEFAULT_MASK _MK_MASK_CONST(0xfffffff) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Indicates if the address region is memory +//mapped versus configuration or IO space. +//1=memory mapped access (PW only) +//0=IO/config access (NWP only) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_FIELD (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_SHIFT) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_RANGE 0:0 +#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_WOFFSET 0x0 +#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_FPCI_BAR2_0 +#define AFI_FPCI_BAR2_0 _MK_ADDR_CONST(0x38) +#define AFI_FPCI_BAR2_0_SECURE 0x0 +#define AFI_FPCI_BAR2_0_WORD_COUNT 0x1 +#define AFI_FPCI_BAR2_0_RESET_VAL _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR2_0_RESET_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR2_0_READ_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR2_0_WRITE_MASK _MK_MASK_CONST(0xfffffff1) +//The start of FPCI address space mapped into the BARi +//range of PCI memory space. The 40-bit FPCI address is determined +//by a a shift left 8 of the value of this register. +#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_SHIFT _MK_SHIFT_CONST(4) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_FIELD (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR2_0_FPCI_BAR2_START_SHIFT) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_RANGE 31:4 +#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_WOFFSET 0x0 +#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_DEFAULT_MASK _MK_MASK_CONST(0xfffffff) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Indicates if the address region is memory +//mapped versus configuration or IO space. +//1=memory mapped access (PW only) +//0=IO/config access (NWP only) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_FIELD (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_SHIFT) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_RANGE 0:0 +#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_WOFFSET 0x0 +#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_FPCI_BAR3_0 +#define AFI_FPCI_BAR3_0 _MK_ADDR_CONST(0x3c) +#define AFI_FPCI_BAR3_0_SECURE 0x0 +#define AFI_FPCI_BAR3_0_WORD_COUNT 0x1 +#define AFI_FPCI_BAR3_0_RESET_VAL _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR3_0_RESET_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR3_0_READ_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR3_0_WRITE_MASK _MK_MASK_CONST(0xfffffff1) +//The start of FPCI address space mapped into the BARi +//range of PCI memory space. The 40-bit FPCI address is determined +//by a a shift left 8 of the value of this register. +#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_SHIFT _MK_SHIFT_CONST(4) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_FIELD (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR3_0_FPCI_BAR3_START_SHIFT) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_RANGE 31:4 +#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_WOFFSET 0x0 +#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_DEFAULT_MASK _MK_MASK_CONST(0xfffffff) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Indicates if the address region is memory +//mapped versus configuration or IO space. +//1=memory mapped access (PW only) +//0=IO/config access (NWP only) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_FIELD (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_SHIFT) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_RANGE 0:0 +#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_WOFFSET 0x0 +#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_FPCI_BAR4_0 +#define AFI_FPCI_BAR4_0 _MK_ADDR_CONST(0x40) +#define AFI_FPCI_BAR4_0_SECURE 0x0 +#define AFI_FPCI_BAR4_0_WORD_COUNT 0x1 +#define AFI_FPCI_BAR4_0_RESET_VAL _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR4_0_RESET_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR4_0_READ_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR4_0_WRITE_MASK _MK_MASK_CONST(0xfffffff1) +//The start of FPCI address space mapped into the BARi +//range of PCI memory space. The 40-bit FPCI address is determined +//by a a shift left 8 of the value of this register. +#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_SHIFT _MK_SHIFT_CONST(4) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_FIELD (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR4_0_FPCI_BAR4_START_SHIFT) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_RANGE 31:4 +#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_WOFFSET 0x0 +#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_DEFAULT_MASK _MK_MASK_CONST(0xfffffff) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Indicates if the address region is memory +//mapped versus configuration or IO space. +//1=memory mapped access (PW only) +//0=IO/config access (NWP only) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_FIELD (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_SHIFT) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_RANGE 0:0 +#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_WOFFSET 0x0 +#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_FPCI_BAR5_0 +#define AFI_FPCI_BAR5_0 _MK_ADDR_CONST(0x44) +#define AFI_FPCI_BAR5_0_SECURE 0x0 +#define AFI_FPCI_BAR5_0_WORD_COUNT 0x1 +#define AFI_FPCI_BAR5_0_RESET_VAL _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR5_0_RESET_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR5_0_READ_MASK _MK_MASK_CONST(0xfffffff1) +#define AFI_FPCI_BAR5_0_WRITE_MASK _MK_MASK_CONST(0xfffffff1) +//The start of FPCI address space mapped into the BARi +//range of PCI memory space. The 40-bit FPCI address is determined +//by a a shift left 8 of the value of this register. +#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_SHIFT _MK_SHIFT_CONST(4) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_FIELD (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR5_0_FPCI_BAR5_START_SHIFT) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_RANGE 31:4 +#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_WOFFSET 0x0 +#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_DEFAULT_MASK _MK_MASK_CONST(0xfffffff) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Indicates if the address region is memory +//mapped versus configuration or IO space. +//1=memory mapped access (PW only) +//0=IO/config access (NWP only) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_FIELD (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_SHIFT) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_RANGE 0:0 +#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_WOFFSET 0x0 +#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_CACHE_BAR0_SZ_0 +#define AFI_CACHE_BAR0_SZ_0 _MK_ADDR_CONST(0x48) +#define AFI_CACHE_BAR0_SZ_0_SECURE 0x0 +#define AFI_CACHE_BAR0_SZ_0_WORD_COUNT 0x1 +#define AFI_CACHE_BAR0_SZ_0_RESET_VAL _MK_MASK_CONST(0x40000) +#define AFI_CACHE_BAR0_SZ_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define AFI_CACHE_BAR0_SZ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR0_SZ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR0_SZ_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define AFI_CACHE_BAR0_SZ_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +//The size of the address range associated with cache BAR is in +//4K increments. Value of 0 signifies BAR is not used. +#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_FIELD (_MK_MASK_CONST(0xfffff) << AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_SHIFT) +#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_RANGE 19:0 +#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_WOFFSET 0x0 +#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_DEFAULT _MK_MASK_CONST(0x40000) +#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_CACHE_BAR0_ST_0 +#define AFI_CACHE_BAR0_ST_0 _MK_ADDR_CONST(0x4c) +#define AFI_CACHE_BAR0_ST_0_SECURE 0x0 +#define AFI_CACHE_BAR0_ST_0_WORD_COUNT 0x1 +#define AFI_CACHE_BAR0_ST_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR0_ST_0_RESET_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_CACHE_BAR0_ST_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR0_ST_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR0_ST_0_READ_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_CACHE_BAR0_ST_0_WRITE_MASK _MK_MASK_CONST(0xfffff000) +//The start of AXI address space for CACHE BAR. +//The AXI initiator address is compared to start/size +//for CACHE BAR to determine if the access is to the BAR. +#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_SHIFT _MK_SHIFT_CONST(12) +#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_FIELD (_MK_MASK_CONST(0xfffff) << AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_SHIFT) +#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_RANGE 31:12 +#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_WOFFSET 0x0 +#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_CACHE_BAR1_SZ_0 +#define AFI_CACHE_BAR1_SZ_0 _MK_ADDR_CONST(0x50) +#define AFI_CACHE_BAR1_SZ_0_SECURE 0x0 +#define AFI_CACHE_BAR1_SZ_0_WORD_COUNT 0x1 +#define AFI_CACHE_BAR1_SZ_0_RESET_VAL _MK_MASK_CONST(0x40000) +#define AFI_CACHE_BAR1_SZ_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define AFI_CACHE_BAR1_SZ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR1_SZ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR1_SZ_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define AFI_CACHE_BAR1_SZ_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +//The size of the address range associated with cache BAR is in +//4K increments. Value of 0 signifies BAR is not used. +#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_FIELD (_MK_MASK_CONST(0xfffff) << AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_SHIFT) +#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_RANGE 19:0 +#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_WOFFSET 0x0 +#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_DEFAULT _MK_MASK_CONST(0x40000) +#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_CACHE_BAR1_ST_0 +#define AFI_CACHE_BAR1_ST_0 _MK_ADDR_CONST(0x54) +#define AFI_CACHE_BAR1_ST_0_SECURE 0x0 +#define AFI_CACHE_BAR1_ST_0_WORD_COUNT 0x1 +#define AFI_CACHE_BAR1_ST_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR1_ST_0_RESET_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_CACHE_BAR1_ST_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR1_ST_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR1_ST_0_READ_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_CACHE_BAR1_ST_0_WRITE_MASK _MK_MASK_CONST(0xfffff000) +//The start of AXI address space for CACHE BAR. +//The AXI initiator address is compared to start/size +//for CACHE BAR to determine if the access is to the BAR. +#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_SHIFT _MK_SHIFT_CONST(12) +#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_FIELD (_MK_MASK_CONST(0xfffff) << AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_SHIFT) +#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_RANGE 31:12 +#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_WOFFSET 0x0 +#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_IO_BAR_SZ_0 +#define AFI_IO_BAR_SZ_0 _MK_ADDR_CONST(0x58) +#define AFI_IO_BAR_SZ_0_SECURE 0x0 +#define AFI_IO_BAR_SZ_0_WORD_COUNT 0x1 +#define AFI_IO_BAR_SZ_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_IO_BAR_SZ_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define AFI_IO_BAR_SZ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_IO_BAR_SZ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_IO_BAR_SZ_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define AFI_IO_BAR_SZ_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +//The size of the address range associated with IO BAR is in +//4K increments. Value of 0 signifies BAR is not used. +#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_FIELD (_MK_MASK_CONST(0xfffff) << AFI_IO_BAR_SZ_0_IO_BAR_SIZE_SHIFT) +#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_RANGE 19:0 +#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_WOFFSET 0x0 +#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_IO_BAR_ST_0 +#define AFI_IO_BAR_ST_0 _MK_ADDR_CONST(0x5c) +#define AFI_IO_BAR_ST_0_SECURE 0x0 +#define AFI_IO_BAR_ST_0_WORD_COUNT 0x1 +#define AFI_IO_BAR_ST_0_RESET_VAL _MK_MASK_CONST(0xfc000000) +#define AFI_IO_BAR_ST_0_RESET_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_IO_BAR_ST_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_IO_BAR_ST_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_IO_BAR_ST_0_READ_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_IO_BAR_ST_0_WRITE_MASK _MK_MASK_CONST(0xfffff000) +//The start of AXI address space for IO BAR. +//The upstream FPCI address starting at 0xFD_FC00_0000 up to +//the range indicated in IO_BAR_SIZE are mapped to start/offset +//for IO BAR. +#define AFI_IO_BAR_ST_0_IO_BAR_START_SHIFT _MK_SHIFT_CONST(12) +#define AFI_IO_BAR_ST_0_IO_BAR_START_FIELD (_MK_MASK_CONST(0xfffff) << AFI_IO_BAR_ST_0_IO_BAR_START_SHIFT) +#define AFI_IO_BAR_ST_0_IO_BAR_START_RANGE 31:12 +#define AFI_IO_BAR_ST_0_IO_BAR_START_WOFFSET 0x0 +#define AFI_IO_BAR_ST_0_IO_BAR_START_DEFAULT _MK_MASK_CONST(0xfc000) +#define AFI_IO_BAR_ST_0_IO_BAR_START_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_IO_BAR_ST_0_IO_BAR_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IO_BAR_ST_0_IO_BAR_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_BAR_SZ_0 +#define AFI_MSI_BAR_SZ_0 _MK_ADDR_CONST(0x60) +#define AFI_MSI_BAR_SZ_0_SECURE 0x0 +#define AFI_MSI_BAR_SZ_0_WORD_COUNT 0x1 +#define AFI_MSI_BAR_SZ_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_BAR_SZ_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define AFI_MSI_BAR_SZ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_BAR_SZ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_BAR_SZ_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define AFI_MSI_BAR_SZ_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +//The size of the address range associated with MSI BAR is +//in 4K increments. Value of 0 signifies BAR is not used. +#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_FIELD (_MK_MASK_CONST(0xfffff) << AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_SHIFT) +#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_RANGE 19:0 +#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_WOFFSET 0x0 +#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_FPCI_BAR_ST_0 +#define AFI_MSI_FPCI_BAR_ST_0 _MK_ADDR_CONST(0x64) +#define AFI_MSI_FPCI_BAR_ST_0_SECURE 0x0 +#define AFI_MSI_FPCI_BAR_ST_0_WORD_COUNT 0x1 +#define AFI_MSI_FPCI_BAR_ST_0_RESET_VAL _MK_MASK_CONST(0x58540000) +#define AFI_MSI_FPCI_BAR_ST_0_RESET_MASK _MK_MASK_CONST(0xfffffff0) +#define AFI_MSI_FPCI_BAR_ST_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_FPCI_BAR_ST_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_FPCI_BAR_ST_0_READ_MASK _MK_MASK_CONST(0xfffffff0) +#define AFI_MSI_FPCI_BAR_ST_0_WRITE_MASK _MK_MASK_CONST(0xfffffff0) +//The start of upstream FPCI address space for MSI BAR. +//The upstream FPCI address is compared to start/1KB range +//for MSI BAR to determine if the access is MSI. Bits 31:4 +//of MSI BAR start correspond to UFPCI address bits 39:12. +#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_SHIFT _MK_SHIFT_CONST(4) +#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_FIELD (_MK_MASK_CONST(0xfffffff) << AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_SHIFT) +#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_RANGE 31:4 +#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_WOFFSET 0x0 +#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_DEFAULT _MK_MASK_CONST(0x5854000) +#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_DEFAULT_MASK _MK_MASK_CONST(0xfffffff) +#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_AXI_BAR_ST_0 +#define AFI_MSI_AXI_BAR_ST_0 _MK_ADDR_CONST(0x68) +#define AFI_MSI_AXI_BAR_ST_0_SECURE 0x0 +#define AFI_MSI_AXI_BAR_ST_0_WORD_COUNT 0x1 +#define AFI_MSI_AXI_BAR_ST_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_AXI_BAR_ST_0_RESET_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_MSI_AXI_BAR_ST_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_AXI_BAR_ST_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_AXI_BAR_ST_0_READ_MASK _MK_MASK_CONST(0xfffff000) +#define AFI_MSI_AXI_BAR_ST_0_WRITE_MASK _MK_MASK_CONST(0xfffff000) +//The start of upstream AXI address space for MSI BAR. +//The upstream FPCI address is compared to start/1KB range +//for MSI BAR to determine if the access is MSI. Bits 31:12 +//of MSI BAR start correspond to AXI address bits 31:12. +#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_SHIFT _MK_SHIFT_CONST(12) +#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_FIELD (_MK_MASK_CONST(0xfffff) << AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_SHIFT) +#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_RANGE 31:12 +#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_WOFFSET 0x0 +#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_VEC0_0 +#define AFI_MSI_VEC0_0 _MK_ADDR_CONST(0x6c) +#define AFI_MSI_VEC0_0_SECURE 0x0 +#define AFI_MSI_VEC0_0_WORD_COUNT 0x1 +#define AFI_MSI_VEC0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to 32 of the possible 256 MSI vectors. +//VECTOR0 corresponds to MSI vectors 31-0. +//Vector7 corresponds to MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the MSI vector +//is set to 1 by hardware if the corresponding enable bit is 1. +//The bit is set to 0 if a 1 is written to its location. +#define AFI_MSI_VEC0_0_MSI_VECTOR0_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_VEC0_0_MSI_VECTOR0_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC0_0_MSI_VECTOR0_SHIFT) +#define AFI_MSI_VEC0_0_MSI_VECTOR0_RANGE 31:0 +#define AFI_MSI_VEC0_0_MSI_VECTOR0_WOFFSET 0x0 +#define AFI_MSI_VEC0_0_MSI_VECTOR0_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC0_0_MSI_VECTOR0_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC0_0_MSI_VECTOR0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC0_0_MSI_VECTOR0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_VEC1_0 +#define AFI_MSI_VEC1_0 _MK_ADDR_CONST(0x70) +#define AFI_MSI_VEC1_0_SECURE 0x0 +#define AFI_MSI_VEC1_0_WORD_COUNT 0x1 +#define AFI_MSI_VEC1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to 32 of the possible 256 MSI vectors. +//VECTOR0 corresponds to MSI vectors 31-0. +//Vector7 corresponds to MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the MSI vector +//is set to 1 by hardware if the corresponding enable bit is 1. +//The bit is set to 0 if a 1 is written to its location. +#define AFI_MSI_VEC1_0_MSI_VECTOR1_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_VEC1_0_MSI_VECTOR1_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC1_0_MSI_VECTOR1_SHIFT) +#define AFI_MSI_VEC1_0_MSI_VECTOR1_RANGE 31:0 +#define AFI_MSI_VEC1_0_MSI_VECTOR1_WOFFSET 0x0 +#define AFI_MSI_VEC1_0_MSI_VECTOR1_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC1_0_MSI_VECTOR1_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC1_0_MSI_VECTOR1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC1_0_MSI_VECTOR1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_VEC2_0 +#define AFI_MSI_VEC2_0 _MK_ADDR_CONST(0x74) +#define AFI_MSI_VEC2_0_SECURE 0x0 +#define AFI_MSI_VEC2_0_WORD_COUNT 0x1 +#define AFI_MSI_VEC2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC2_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to 32 of the possible 256 MSI vectors. +//VECTOR0 corresponds to MSI vectors 31-0. +//Vector7 corresponds to MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the MSI vector +//is set to 1 by hardware if the corresponding enable bit is 1. +//The bit is set to 0 if a 1 is written to its location. +#define AFI_MSI_VEC2_0_MSI_VECTOR2_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_VEC2_0_MSI_VECTOR2_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC2_0_MSI_VECTOR2_SHIFT) +#define AFI_MSI_VEC2_0_MSI_VECTOR2_RANGE 31:0 +#define AFI_MSI_VEC2_0_MSI_VECTOR2_WOFFSET 0x0 +#define AFI_MSI_VEC2_0_MSI_VECTOR2_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC2_0_MSI_VECTOR2_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC2_0_MSI_VECTOR2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC2_0_MSI_VECTOR2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_VEC3_0 +#define AFI_MSI_VEC3_0 _MK_ADDR_CONST(0x78) +#define AFI_MSI_VEC3_0_SECURE 0x0 +#define AFI_MSI_VEC3_0_WORD_COUNT 0x1 +#define AFI_MSI_VEC3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC3_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC3_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC3_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to 32 of the possible 256 MSI vectors. +//VECTOR0 corresponds to MSI vectors 31-0. +//Vector7 corresponds to MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the MSI vector +//is set to 1 by hardware if the corresponding enable bit is 1. +//The bit is set to 0 if a 1 is written to its location. +#define AFI_MSI_VEC3_0_MSI_VECTOR3_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_VEC3_0_MSI_VECTOR3_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC3_0_MSI_VECTOR3_SHIFT) +#define AFI_MSI_VEC3_0_MSI_VECTOR3_RANGE 31:0 +#define AFI_MSI_VEC3_0_MSI_VECTOR3_WOFFSET 0x0 +#define AFI_MSI_VEC3_0_MSI_VECTOR3_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC3_0_MSI_VECTOR3_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC3_0_MSI_VECTOR3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC3_0_MSI_VECTOR3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_VEC4_0 +#define AFI_MSI_VEC4_0 _MK_ADDR_CONST(0x7c) +#define AFI_MSI_VEC4_0_SECURE 0x0 +#define AFI_MSI_VEC4_0_WORD_COUNT 0x1 +#define AFI_MSI_VEC4_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC4_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC4_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC4_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to 32 of the possible 256 MSI vectors. +//VECTOR0 corresponds to MSI vectors 31-0. +//Vector7 corresponds to MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the MSI vector +//is set to 1 by hardware if the corresponding enable bit is 1. +//The bit is set to 0 if a 1 is written to its location. +#define AFI_MSI_VEC4_0_MSI_VECTOR4_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_VEC4_0_MSI_VECTOR4_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC4_0_MSI_VECTOR4_SHIFT) +#define AFI_MSI_VEC4_0_MSI_VECTOR4_RANGE 31:0 +#define AFI_MSI_VEC4_0_MSI_VECTOR4_WOFFSET 0x0 +#define AFI_MSI_VEC4_0_MSI_VECTOR4_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC4_0_MSI_VECTOR4_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC4_0_MSI_VECTOR4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC4_0_MSI_VECTOR4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_VEC5_0 +#define AFI_MSI_VEC5_0 _MK_ADDR_CONST(0x80) +#define AFI_MSI_VEC5_0_SECURE 0x0 +#define AFI_MSI_VEC5_0_WORD_COUNT 0x1 +#define AFI_MSI_VEC5_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC5_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC5_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC5_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to 32 of the possible 256 MSI vectors. +//VECTOR0 corresponds to MSI vectors 31-0. +//Vector7 corresponds to MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the MSI vector +//is set to 1 by hardware if the corresponding enable bit is 1. +//The bit is set to 0 if a 1 is written to its location. +#define AFI_MSI_VEC5_0_MSI_VECTOR5_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_VEC5_0_MSI_VECTOR5_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC5_0_MSI_VECTOR5_SHIFT) +#define AFI_MSI_VEC5_0_MSI_VECTOR5_RANGE 31:0 +#define AFI_MSI_VEC5_0_MSI_VECTOR5_WOFFSET 0x0 +#define AFI_MSI_VEC5_0_MSI_VECTOR5_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC5_0_MSI_VECTOR5_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC5_0_MSI_VECTOR5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC5_0_MSI_VECTOR5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_VEC6_0 +#define AFI_MSI_VEC6_0 _MK_ADDR_CONST(0x84) +#define AFI_MSI_VEC6_0_SECURE 0x0 +#define AFI_MSI_VEC6_0_WORD_COUNT 0x1 +#define AFI_MSI_VEC6_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC6_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC6_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC6_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to 32 of the possible 256 MSI vectors. +//VECTOR0 corresponds to MSI vectors 31-0. +//Vector7 corresponds to MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the MSI vector +//is set to 1 by hardware if the corresponding enable bit is 1. +//The bit is set to 0 if a 1 is written to its location. +#define AFI_MSI_VEC6_0_MSI_VECTOR6_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_VEC6_0_MSI_VECTOR6_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC6_0_MSI_VECTOR6_SHIFT) +#define AFI_MSI_VEC6_0_MSI_VECTOR6_RANGE 31:0 +#define AFI_MSI_VEC6_0_MSI_VECTOR6_WOFFSET 0x0 +#define AFI_MSI_VEC6_0_MSI_VECTOR6_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC6_0_MSI_VECTOR6_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC6_0_MSI_VECTOR6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC6_0_MSI_VECTOR6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_VEC7_0 +#define AFI_MSI_VEC7_0 _MK_ADDR_CONST(0x88) +#define AFI_MSI_VEC7_0_SECURE 0x0 +#define AFI_MSI_VEC7_0_WORD_COUNT 0x1 +#define AFI_MSI_VEC7_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC7_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC7_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC7_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC7_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to 32 of the possible 256 MSI vectors. +//VECTOR0 corresponds to MSI vectors 31-0. +//Vector7 corresponds to MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the MSI vector +//is set to 1 by hardware if the corresponding enable bit is 1. +//The bit is set to 0 if a 1 is written to its location. +#define AFI_MSI_VEC7_0_MSI_VECTOR7_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_VEC7_0_MSI_VECTOR7_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC7_0_MSI_VECTOR7_SHIFT) +#define AFI_MSI_VEC7_0_MSI_VECTOR7_RANGE 31:0 +#define AFI_MSI_VEC7_0_MSI_VECTOR7_WOFFSET 0x0 +#define AFI_MSI_VEC7_0_MSI_VECTOR7_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC7_0_MSI_VECTOR7_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_VEC7_0_MSI_VECTOR7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_VEC7_0_MSI_VECTOR7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_EN_VEC0_0 +#define AFI_MSI_EN_VEC0_0 _MK_ADDR_CONST(0x8c) +#define AFI_MSI_EN_VEC0_0_SECURE 0x0 +#define AFI_MSI_EN_VEC0_0_WORD_COUNT 0x1 +#define AFI_MSI_EN_VEC0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to the enable bit for 32 +//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds +//to enable bits for MSI vectors 31-0. Vector7 corresponds +//to enable bits for MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the +//MSI vector is set to 1 by hardware if the corresponding +//enable bit is 1. +#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_SHIFT) +#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_RANGE 31:0 +#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_WOFFSET 0x0 +#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_EN_VEC1_0 +#define AFI_MSI_EN_VEC1_0 _MK_ADDR_CONST(0x90) +#define AFI_MSI_EN_VEC1_0_SECURE 0x0 +#define AFI_MSI_EN_VEC1_0_WORD_COUNT 0x1 +#define AFI_MSI_EN_VEC1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to the enable bit for 32 +//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds +//to enable bits for MSI vectors 31-0. Vector7 corresponds +//to enable bits for MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the +//MSI vector is set to 1 by hardware if the corresponding +//enable bit is 1. +#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_SHIFT) +#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_RANGE 31:0 +#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_WOFFSET 0x0 +#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_EN_VEC2_0 +#define AFI_MSI_EN_VEC2_0 _MK_ADDR_CONST(0x94) +#define AFI_MSI_EN_VEC2_0_SECURE 0x0 +#define AFI_MSI_EN_VEC2_0_WORD_COUNT 0x1 +#define AFI_MSI_EN_VEC2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC2_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to the enable bit for 32 +//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds +//to enable bits for MSI vectors 31-0. Vector7 corresponds +//to enable bits for MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the +//MSI vector is set to 1 by hardware if the corresponding +//enable bit is 1. +#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_SHIFT) +#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_RANGE 31:0 +#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_WOFFSET 0x0 +#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_EN_VEC3_0 +#define AFI_MSI_EN_VEC3_0 _MK_ADDR_CONST(0x98) +#define AFI_MSI_EN_VEC3_0_SECURE 0x0 +#define AFI_MSI_EN_VEC3_0_WORD_COUNT 0x1 +#define AFI_MSI_EN_VEC3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC3_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC3_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC3_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to the enable bit for 32 +//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds +//to enable bits for MSI vectors 31-0. Vector7 corresponds +//to enable bits for MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the +//MSI vector is set to 1 by hardware if the corresponding +//enable bit is 1. +#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_SHIFT) +#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_RANGE 31:0 +#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_WOFFSET 0x0 +#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_EN_VEC4_0 +#define AFI_MSI_EN_VEC4_0 _MK_ADDR_CONST(0x9c) +#define AFI_MSI_EN_VEC4_0_SECURE 0x0 +#define AFI_MSI_EN_VEC4_0_WORD_COUNT 0x1 +#define AFI_MSI_EN_VEC4_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC4_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC4_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC4_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to the enable bit for 32 +//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds +//to enable bits for MSI vectors 31-0. Vector7 corresponds +//to enable bits for MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the +//MSI vector is set to 1 by hardware if the corresponding +//enable bit is 1. +#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_SHIFT) +#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_RANGE 31:0 +#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_WOFFSET 0x0 +#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_EN_VEC5_0 +#define AFI_MSI_EN_VEC5_0 _MK_ADDR_CONST(0xa0) +#define AFI_MSI_EN_VEC5_0_SECURE 0x0 +#define AFI_MSI_EN_VEC5_0_WORD_COUNT 0x1 +#define AFI_MSI_EN_VEC5_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC5_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC5_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC5_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to the enable bit for 32 +//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds +//to enable bits for MSI vectors 31-0. Vector7 corresponds +//to enable bits for MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the +//MSI vector is set to 1 by hardware if the corresponding +//enable bit is 1. +#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_SHIFT) +#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_RANGE 31:0 +#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_WOFFSET 0x0 +#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_EN_VEC6_0 +#define AFI_MSI_EN_VEC6_0 _MK_ADDR_CONST(0xa4) +#define AFI_MSI_EN_VEC6_0_SECURE 0x0 +#define AFI_MSI_EN_VEC6_0_WORD_COUNT 0x1 +#define AFI_MSI_EN_VEC6_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC6_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC6_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC6_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to the enable bit for 32 +//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds +//to enable bits for MSI vectors 31-0. Vector7 corresponds +//to enable bits for MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the +//MSI vector is set to 1 by hardware if the corresponding +//enable bit is 1. +#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_SHIFT) +#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_RANGE 31:0 +#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_WOFFSET 0x0 +#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_MSI_EN_VEC7_0 +#define AFI_MSI_EN_VEC7_0 _MK_ADDR_CONST(0xa8) +#define AFI_MSI_EN_VEC7_0_SECURE 0x0 +#define AFI_MSI_EN_VEC7_0_WORD_COUNT 0x1 +#define AFI_MSI_EN_VEC7_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC7_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC7_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC7_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC7_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Each vector register corresponds to the enable bit for 32 +//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds +//to enable bits for MSI vectors 31-0. Vector7 corresponds +//to enable bits for MSI vectors 255-223. +//When an upstream MSI is sent, the bit corresponding to the +//MSI vector is set to 1 by hardware if the corresponding +//enable bit is 1. +#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_SHIFT _MK_SHIFT_CONST(0) +#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_SHIFT) +#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_RANGE 31:0 +#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_WOFFSET 0x0 +#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_CONFIGURATION_0 +#define AFI_CONFIGURATION_0 _MK_ADDR_CONST(0xac) +#define AFI_CONFIGURATION_0_SECURE 0x0 +#define AFI_CONFIGURATION_0_WORD_COUNT 0x1 +#define AFI_CONFIGURATION_0_RESET_VAL _MK_MASK_CONST(0x8e04) +#define AFI_CONFIGURATION_0_RESET_MASK _MK_MASK_CONST(0xff3f) +#define AFI_CONFIGURATION_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_READ_MASK _MK_MASK_CONST(0xff3f) +#define AFI_CONFIGURATION_0_WRITE_MASK _MK_MASK_CONST(0xc03f) +//When the PCI device block is disabled, it is completely invisible +//on the PCI bus, i.e. it doesn't even process PCI configuration accesses. +#define AFI_CONFIGURATION_0_EN_FPCI_SHIFT _MK_SHIFT_CONST(0) +#define AFI_CONFIGURATION_0_EN_FPCI_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_EN_FPCI_SHIFT) +#define AFI_CONFIGURATION_0_EN_FPCI_RANGE 0:0 +#define AFI_CONFIGURATION_0_EN_FPCI_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_EN_FPCI_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_EN_FPCI_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_EN_FPCI_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_EN_FPCI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//CYA - input to downstream FPCI. +//Allow downstream FPCI reads to pass writes. +#define AFI_CONFIGURATION_0_DFPCI_PASSPW_SHIFT _MK_SHIFT_CONST(1) +#define AFI_CONFIGURATION_0_DFPCI_PASSPW_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_DFPCI_PASSPW_SHIFT) +#define AFI_CONFIGURATION_0_DFPCI_PASSPW_RANGE 1:1 +#define AFI_CONFIGURATION_0_DFPCI_PASSPW_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_DFPCI_PASSPW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_DFPCI_PASSPW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_DFPCI_PASSPW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_DFPCI_PASSPW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//CYA - input to downstream FPCI. +//Allow downstream FPCI responses to pass writes +#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_SHIFT _MK_SHIFT_CONST(2) +#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_SHIFT) +#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_RANGE 2:2 +#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//CYA - used for downstream FPCI. +//Allow downstream FPCI PWs to pass NPWs. +#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_SHIFT _MK_SHIFT_CONST(3) +#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_SHIFT) +#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_RANGE 3:3 +#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//CYA - used for upstream FPCI. +//Allow upstream FPCI PWs to pass NPWs. +#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_SHIFT _MK_SHIFT_CONST(4) +#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_SHIFT) +#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_RANGE 4:4 +#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//CYA - input to upstream FPCI. +//Allow upstream FPCI reads to pass writes. +#define AFI_CONFIGURATION_0_UFPCI_PASSPW_SHIFT _MK_SHIFT_CONST(5) +#define AFI_CONFIGURATION_0_UFPCI_PASSPW_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_UFPCI_PASSPW_SHIFT) +#define AFI_CONFIGURATION_0_UFPCI_PASSPW_RANGE 5:5 +#define AFI_CONFIGURATION_0_UFPCI_PASSPW_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_UFPCI_PASSPW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_UFPCI_PASSPW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_UFPCI_PASSPW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_UFPCI_PASSPW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//This read-only bit provides status on whether PCIe is strapped +//as a root port or endpoint. The value of this bit is 1b (endpoint) +//if production mode is 0b (disabled) and memory strap_ram_code[0] is 1b. +#define AFI_CONFIGURATION_0_ENDPT_MODE_SHIFT _MK_SHIFT_CONST(8) +#define AFI_CONFIGURATION_0_ENDPT_MODE_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_ENDPT_MODE_SHIFT) +#define AFI_CONFIGURATION_0_ENDPT_MODE_RANGE 8:8 +#define AFI_CONFIGURATION_0_ENDPT_MODE_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_ENDPT_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_ENDPT_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_ENDPT_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_ENDPT_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//This read-only bit provides status on whether MSI Vector registers +//have any active bits valid or not +#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_SHIFT _MK_SHIFT_CONST(9) +#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_MSI_VEC_EMPTY_SHIFT) +#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_RANGE 9:9 +#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//This read-only bit provides status writes to AFI target. +//A value of 1b indicates there are no outstanding writes to downstream FPCI. +#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_SHIFT _MK_SHIFT_CONST(10) +#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_SHIFT) +#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_RANGE 10:10 +#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//This read-only bit provides status reads to AFI target. +//A value of 1b indicates there are no outstanding reads to downstream FPCI. +#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_SHIFT _MK_SHIFT_CONST(11) +#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_TARGET_READ_IDLE_SHIFT) +#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_RANGE 11:11 +#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//This read-only bit is 0 when a card is present in PCIE slot 0 +#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_SHIFT _MK_SHIFT_CONST(12) +#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_SHIFT) +#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_RANGE 12:12 +#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//This read-only bit is 0 when a card is present in PCIE slot 1 +#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_SHIFT _MK_SHIFT_CONST(13) +#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_SHIFT) +#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_RANGE 13:13 +#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//CYA - used to en(dis)able the handling of interleaved write requests on mselect +#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_SHIFT _MK_SHIFT_CONST(14) +#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_WR_INTRLV_CYA_SHIFT) +#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_RANGE 14:14 +#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//CYA - used to en(dis)able the handling of write data ahead of requests on mselect +#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_SHIFT _MK_SHIFT_CONST(15) +#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_FIELD (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_WDATA_LEAD_CYA_SHIFT) +#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_RANGE 15:15 +#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_WOFFSET 0x0 +#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_FPCI_ERROR_MASKS_0 +#define AFI_FPCI_ERROR_MASKS_0 _MK_ADDR_CONST(0xb0) +#define AFI_FPCI_ERROR_MASKS_0_SECURE 0x0 +#define AFI_FPCI_ERROR_MASKS_0_WORD_COUNT 0x1 +#define AFI_FPCI_ERROR_MASKS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_FPCI_ERROR_MASKS_0_RESET_MASK _MK_MASK_CONST(0x7) +#define AFI_FPCI_ERROR_MASKS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_FPCI_ERROR_MASKS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_FPCI_ERROR_MASKS_0_READ_MASK _MK_MASK_CONST(0x7) +#define AFI_FPCI_ERROR_MASKS_0_WRITE_MASK _MK_MASK_CONST(0x7) +//This bit allows FPCI error to be forwarded to AXI response when FPCI error response +//indicates Target Abort. 1 = forward error, 0 = return AXI OKAY response (2'b0) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_SHIFT _MK_SHIFT_CONST(0) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_FIELD (_MK_MASK_CONST(0x1) << AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_SHIFT) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_RANGE 0:0 +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_WOFFSET 0x0 +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//This bit allows FPCI error to be forwarded to AXI response when FPCI error response +//indicates Data Error. 1 = forward error, 0 = return AXI OKAY response (2'b0) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_SHIFT _MK_SHIFT_CONST(1) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_FIELD (_MK_MASK_CONST(0x1) << AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_SHIFT) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_RANGE 1:1 +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_WOFFSET 0x0 +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//This bit allows FPCI error to be forwarded to AXI response when FPCI error response +//indicates Master Abort. 1 = forward error, 0 = return AXI OKAY response (2'b0) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_SHIFT _MK_SHIFT_CONST(2) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_FIELD (_MK_MASK_CONST(0x1) << AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_SHIFT) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_RANGE 2:2 +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_WOFFSET 0x0 +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_INTR_MASK_0 +#define AFI_INTR_MASK_0 _MK_ADDR_CONST(0xb4) +#define AFI_INTR_MASK_0_SECURE 0x0 +#define AFI_INTR_MASK_0_WORD_COUNT 0x1 +#define AFI_INTR_MASK_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_INTR_MASK_0_RESET_MASK _MK_MASK_CONST(0x101) +#define AFI_INTR_MASK_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_INTR_MASK_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_INTR_MASK_0_READ_MASK _MK_MASK_CONST(0x101) +#define AFI_INTR_MASK_0_WRITE_MASK _MK_MASK_CONST(0x101) +//Interrupt to MPCORE gated by mask. +#define AFI_INTR_MASK_0_INT_MASK_SHIFT _MK_SHIFT_CONST(0) +#define AFI_INTR_MASK_0_INT_MASK_FIELD (_MK_MASK_CONST(0x1) << AFI_INTR_MASK_0_INT_MASK_SHIFT) +#define AFI_INTR_MASK_0_INT_MASK_RANGE 0:0 +#define AFI_INTR_MASK_0_INT_MASK_WOFFSET 0x0 +#define AFI_INTR_MASK_0_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_INTR_MASK_0_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_INTR_MASK_0_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_INTR_MASK_0_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//MSI to MPCORE gated by mask. +#define AFI_INTR_MASK_0_MSI_MASK_SHIFT _MK_SHIFT_CONST(8) +#define AFI_INTR_MASK_0_MSI_MASK_FIELD (_MK_MASK_CONST(0x1) << AFI_INTR_MASK_0_MSI_MASK_SHIFT) +#define AFI_INTR_MASK_0_MSI_MASK_RANGE 8:8 +#define AFI_INTR_MASK_0_MSI_MASK_WOFFSET 0x0 +#define AFI_INTR_MASK_0_MSI_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_INTR_MASK_0_MSI_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_INTR_MASK_0_MSI_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_INTR_MASK_0_MSI_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_INTR_CODE_0 +#define AFI_INTR_CODE_0 _MK_ADDR_CONST(0xb8) +#define AFI_INTR_CODE_0_SECURE 0x0 +#define AFI_INTR_CODE_0_WORD_COUNT 0x1 +#define AFI_INTR_CODE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_INTR_CODE_0_RESET_MASK _MK_MASK_CONST(0xf) +#define AFI_INTR_CODE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_INTR_CODE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_INTR_CODE_0_READ_MASK _MK_MASK_CONST(0xf) +#define AFI_INTR_CODE_0_WRITE_MASK _MK_MASK_CONST(0xf) +//Eight interrupt codes +//If the code is 0, logging of the next interrupt is enabled +#define AFI_INTR_CODE_0_INT_CODE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_INTR_CODE_0_INT_CODE_FIELD (_MK_MASK_CONST(0xf) << AFI_INTR_CODE_0_INT_CODE_SHIFT) +#define AFI_INTR_CODE_0_INT_CODE_RANGE 3:0 +#define AFI_INTR_CODE_0_INT_CODE_WOFFSET 0x0 +#define AFI_INTR_CODE_0_INT_CODE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_INTR_CODE_0_INT_CODE_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define AFI_INTR_CODE_0_INT_CODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_INTR_CODE_0_INT_CODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_CLEAR _MK_ENUM_CONST(0) // //Clear interrupt code + +#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_INI_SLVERR _MK_ENUM_CONST(1) // //Interrupt code for MPCORE AXI SLVERR response to AFI + +#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_INI_DECERR _MK_ENUM_CONST(2) // //Interrupt code for MPCORE AXI DECERR response to AFI + +#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_TGT_SLVERR _MK_ENUM_CONST(3) // //Interrupt code for PCIE endpoint FPCI target abort or data error +//response to AFI + +#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_TGT_DECERR _MK_ENUM_CONST(4) // //Interrupt code for PCIE2 FPCI master abort response to AFI + +#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_TGT_WRERR _MK_ENUM_CONST(5) // //Interrupt code for bufferable write to non-posted write address region + +#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_SM_MSG _MK_ENUM_CONST(6) // //Interrupt code for PCIE2 system management message + +#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_DFPCI_DECERR _MK_ENUM_CONST(7) // //Interrupt code for PCIE2 response to downstream request when +//downstream FPCI addresss does not fall in a claimable downstream region + +#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_AXI_DECERR _MK_ENUM_CONST(8) // //Interrupt code for AFI response to downstream request when +//mselect AXI addresss does not fall in any of AFI downstream BARs + +#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_FPCI_TIMEOUT _MK_ENUM_CONST(9) // //Interrupt code for FPCI Timeout + + + +// Register AFI_INTR_SIGNATURE_0 +#define AFI_INTR_SIGNATURE_0 _MK_ADDR_CONST(0xbc) +#define AFI_INTR_SIGNATURE_0_SECURE 0x0 +#define AFI_INTR_SIGNATURE_0_WORD_COUNT 0x1 +#define AFI_INTR_SIGNATURE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_INTR_SIGNATURE_0_RESET_MASK _MK_MASK_CONST(0xfffffffd) +#define AFI_INTR_SIGNATURE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_INTR_SIGNATURE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_INTR_SIGNATURE_0_READ_MASK _MK_MASK_CONST(0xfffffffd) +#define AFI_INTR_SIGNATURE_0_WRITE_MASK _MK_MASK_CONST(0xfffffffd) +//Indicates direction of the AXI/FPCI transaction. 1=rd/0=wr +//If signature type is 6 (sideband message), this field is 1. +#define AFI_INTR_SIGNATURE_0_DIR_SHIFT _MK_SHIFT_CONST(0) +#define AFI_INTR_SIGNATURE_0_DIR_FIELD (_MK_MASK_CONST(0x1) << AFI_INTR_SIGNATURE_0_DIR_SHIFT) +#define AFI_INTR_SIGNATURE_0_DIR_RANGE 0:0 +#define AFI_INTR_SIGNATURE_0_DIR_WOFFSET 0x0 +#define AFI_INTR_SIGNATURE_0_DIR_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_INTR_SIGNATURE_0_DIR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_INTR_SIGNATURE_0_DIR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_INTR_SIGNATURE_0_DIR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_INTR_SIGNATURE_0_DIR_WRITE _MK_ENUM_CONST(0) // //Interrupt due to a write transaction + +#define AFI_INTR_SIGNATURE_0_DIR_READ _MK_ENUM_CONST(1) // //Interrupt due to a read transaction + + +//For interrupt codes 1-5/7-8, it contains address bits [31:2], +//either in FPCI memory space or AXI space. If interrupt code is 6, +//the information field INT_INFO[12:0] contain sideband information +//{sideband unitid, 3'b0, tms02sm_msg[4:0]}. +//For FPCI generated errors, the info contains FPCI address. +//For AXI/AFI generated errors, the info contains AXI address. +#define AFI_INTR_SIGNATURE_0_INT_INFO_SHIFT _MK_SHIFT_CONST(2) +#define AFI_INTR_SIGNATURE_0_INT_INFO_FIELD (_MK_MASK_CONST(0x3fffffff) << AFI_INTR_SIGNATURE_0_INT_INFO_SHIFT) +#define AFI_INTR_SIGNATURE_0_INT_INFO_RANGE 31:2 +#define AFI_INTR_SIGNATURE_0_INT_INFO_WOFFSET 0x0 +#define AFI_INTR_SIGNATURE_0_INT_INFO_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_INTR_SIGNATURE_0_INT_INFO_DEFAULT_MASK _MK_MASK_CONST(0x3fffffff) +#define AFI_INTR_SIGNATURE_0_INT_INFO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_INTR_SIGNATURE_0_INT_INFO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_UPPER_FPCI_ADDR_0 +#define AFI_UPPER_FPCI_ADDR_0 _MK_ADDR_CONST(0xc0) +#define AFI_UPPER_FPCI_ADDR_0_SECURE 0x0 +#define AFI_UPPER_FPCI_ADDR_0_WORD_COUNT 0x1 +#define AFI_UPPER_FPCI_ADDR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_UPPER_FPCI_ADDR_0_RESET_MASK _MK_MASK_CONST(0xff) +#define AFI_UPPER_FPCI_ADDR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_UPPER_FPCI_ADDR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_UPPER_FPCI_ADDR_0_READ_MASK _MK_MASK_CONST(0xff) +#define AFI_UPPER_FPCI_ADDR_0_WRITE_MASK _MK_MASK_CONST(0xff) +//These 8 bits are the upper byte of captured FPCI address (bits[39:32]) +//when interrupt code is 3, 4 or 7. These bits determine the region +//in the Hypertransport Address Map that was accessed. This map +//is described in section 3.2.4 of the AFI IAS. +#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_SHIFT _MK_SHIFT_CONST(0) +#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_FIELD (_MK_MASK_CONST(0xff) << AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_SHIFT) +#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_RANGE 7:0 +#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_WOFFSET 0x0 +#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_SM_INTR_ENABLE_0 +#define AFI_SM_INTR_ENABLE_0 _MK_ADDR_CONST(0xc4) +#define AFI_SM_INTR_ENABLE_0_SECURE 0x0 +#define AFI_SM_INTR_ENABLE_0_WORD_COUNT 0x1 +#define AFI_SM_INTR_ENABLE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_SM_INTR_ENABLE_0_RESET_MASK _MK_MASK_CONST(0x7fff) +#define AFI_SM_INTR_ENABLE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_SM_INTR_ENABLE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_SM_INTR_ENABLE_0_READ_MASK _MK_MASK_CONST(0x7fff) +#define AFI_SM_INTR_ENABLE_0_WRITE_MASK _MK_MASK_CONST(0x7fff) +//Each of the bits in this register correspond to enabling the +//associated message shown in the system message table in 3.2.10 +//Enable bits for interrupt code 6 of table in section 8.1.3 +#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_FIELD (_MK_MASK_CONST(0x7fff) << AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_SHIFT) +#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_RANGE 14:0 +#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_WOFFSET 0x0 +#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AFI_INTR_ENABLE_0 +#define AFI_AFI_INTR_ENABLE_0 _MK_ADDR_CONST(0xc8) +#define AFI_AFI_INTR_ENABLE_0_SECURE 0x0 +#define AFI_AFI_INTR_ENABLE_0_WORD_COUNT 0x1 +#define AFI_AFI_INTR_ENABLE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_RESET_MASK _MK_MASK_CONST(0xff) +#define AFI_AFI_INTR_ENABLE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_READ_MASK _MK_MASK_CONST(0xff) +#define AFI_AFI_INTR_ENABLE_0_WRITE_MASK _MK_MASK_CONST(0xff) +//Enable bit for interrupt code 1 +#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_SHIFT _MK_SHIFT_CONST(0) +#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_FIELD (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_SHIFT) +#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_RANGE 0:0 +#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_WOFFSET 0x0 +#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Enable bit for interrupt code 2 +#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_SHIFT _MK_SHIFT_CONST(1) +#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_FIELD (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_SHIFT) +#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_RANGE 1:1 +#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_WOFFSET 0x0 +#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Enable bit for interrupt code 3 +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_SHIFT _MK_SHIFT_CONST(2) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_FIELD (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_SHIFT) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_RANGE 2:2 +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_WOFFSET 0x0 +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Enable bit for interrupt code 4 +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_SHIFT _MK_SHIFT_CONST(3) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_FIELD (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_SHIFT) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_RANGE 3:3 +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_WOFFSET 0x0 +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Enable bit for interrupt code 5 +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_SHIFT _MK_SHIFT_CONST(4) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_FIELD (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_SHIFT) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_RANGE 4:4 +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_WOFFSET 0x0 +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Enable bit for interrupt code 7 +#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_SHIFT _MK_SHIFT_CONST(5) +#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_FIELD (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_SHIFT) +#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_RANGE 5:5 +#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_WOFFSET 0x0 +#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Enable bit for interrupt code 8 +#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_SHIFT _MK_SHIFT_CONST(6) +#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_FIELD (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_SHIFT) +#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_RANGE 6:6 +#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_WOFFSET 0x0 +#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Enable bit for interrupt code 9 +#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_SHIFT _MK_SHIFT_CONST(7) +#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_FIELD (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_SHIFT) +#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_RANGE 7:7 +#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_WOFFSET 0x0 +#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_AUSER_OVERRIDE_0 +#define AFI_AUSER_OVERRIDE_0 _MK_ADDR_CONST(0xcc) +#define AFI_AUSER_OVERRIDE_0_SECURE 0x0 +#define AFI_AUSER_OVERRIDE_0_WORD_COUNT 0x1 +#define AFI_AUSER_OVERRIDE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_AUSER_OVERRIDE_0_RESET_MASK _MK_MASK_CONST(0x8000001f) +#define AFI_AUSER_OVERRIDE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_AUSER_OVERRIDE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_AUSER_OVERRIDE_0_READ_MASK _MK_MASK_CONST(0x8000001f) +#define AFI_AUSER_OVERRIDE_0_WRITE_MASK _MK_MASK_CONST(0x8000001f) +//Programmable value to drive on to AXI initiator AUSER fields +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_SHIFT _MK_SHIFT_CONST(0) +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_FIELD (_MK_MASK_CONST(0x1f) << AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_SHIFT) +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_RANGE 4:0 +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_WOFFSET 0x0 +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_DEFAULT_MASK _MK_MASK_CONST(0x1f) +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Enables value in override register to be driven on AXI initiator +//AUSER when in preproduction mode. +//1=drive AUSER override value (preproduction mode only) +//0=drive AUSER normally +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_SHIFT _MK_SHIFT_CONST(31) +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_FIELD (_MK_MASK_CONST(0x1) << AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_SHIFT) +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_RANGE 31:31 +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_WOFFSET 0x0 +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_ACACHE_OVERRIDE_0 +#define AFI_ACACHE_OVERRIDE_0 _MK_ADDR_CONST(0xd0) +#define AFI_ACACHE_OVERRIDE_0_SECURE 0x0 +#define AFI_ACACHE_OVERRIDE_0_WORD_COUNT 0x1 +#define AFI_ACACHE_OVERRIDE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_ACACHE_OVERRIDE_0_RESET_MASK _MK_MASK_CONST(0x8000000f) +#define AFI_ACACHE_OVERRIDE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_ACACHE_OVERRIDE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_ACACHE_OVERRIDE_0_READ_MASK _MK_MASK_CONST(0x8000000f) +#define AFI_ACACHE_OVERRIDE_0_WRITE_MASK _MK_MASK_CONST(0x8000000f) +//Programmable value to drive on to AXI initiator ACACHE fields +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_SHIFT _MK_SHIFT_CONST(0) +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_FIELD (_MK_MASK_CONST(0xf) << AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_SHIFT) +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_RANGE 3:0 +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_WOFFSET 0x0 +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Enables value in override register to be driven on AXI initiator +//ACACHE when in preproduction mode. +//1=drive ACACHE override value (preproduction mode only) +//0=drive ACACHE normally +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_SHIFT _MK_SHIFT_CONST(31) +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_FIELD (_MK_MASK_CONST(0x1) << AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_SHIFT) +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_RANGE 31:31 +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_WOFFSET 0x0 +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_APROT_OVERRIDE_0 +#define AFI_APROT_OVERRIDE_0 _MK_ADDR_CONST(0xd4) +#define AFI_APROT_OVERRIDE_0_SECURE 0x0 +#define AFI_APROT_OVERRIDE_0_WORD_COUNT 0x1 +#define AFI_APROT_OVERRIDE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_APROT_OVERRIDE_0_RESET_MASK _MK_MASK_CONST(0x80000007) +#define AFI_APROT_OVERRIDE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_APROT_OVERRIDE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_APROT_OVERRIDE_0_READ_MASK _MK_MASK_CONST(0x80000007) +#define AFI_APROT_OVERRIDE_0_WRITE_MASK _MK_MASK_CONST(0x80000007) +//Programmable value to drive on to AXI initiator APROT fields +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_SHIFT _MK_SHIFT_CONST(0) +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_FIELD (_MK_MASK_CONST(0x7) << AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_SHIFT) +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_RANGE 2:0 +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_WOFFSET 0x0 +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Enables value in override register to be driven on AXI initiator +//APROT when in preproduction mode. +//1=drive APROT override value (preproduction mode only) +//0=drive APROT normally +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_SHIFT _MK_SHIFT_CONST(31) +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_FIELD (_MK_MASK_CONST(0x1) << AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_SHIFT) +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_RANGE 31:31 +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_WOFFSET 0x0 +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_FPCI_TIMEOUT_0 +#define AFI_FPCI_TIMEOUT_0 _MK_ADDR_CONST(0xd8) +#define AFI_FPCI_TIMEOUT_0_SECURE 0x0 +#define AFI_FPCI_TIMEOUT_0_WORD_COUNT 0x1 +#define AFI_FPCI_TIMEOUT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_FPCI_TIMEOUT_0_RESET_MASK _MK_MASK_CONST(0x800fffff) +#define AFI_FPCI_TIMEOUT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_FPCI_TIMEOUT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_FPCI_TIMEOUT_0_READ_MASK _MK_MASK_CONST(0x800fffff) +#define AFI_FPCI_TIMEOUT_0_WRITE_MASK _MK_MASK_CONST(0x800fffff) +//SM (system management) threshold specifying how long to wait +//for response from FPCI before declaring it timeout +#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_SHIFT _MK_SHIFT_CONST(0) +#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_FIELD (_MK_MASK_CONST(0xfffff) << AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_SHIFT) +#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_RANGE 19:0 +#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_WOFFSET 0x0 +#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) timeout enable +#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_SHIFT _MK_SHIFT_CONST(31) +#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_FIELD (_MK_MASK_CONST(0x1) << AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_SHIFT) +#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_RANGE 31:31 +#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_WOFFSET 0x0 +#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_IDDQ_MODE_0 +#define AFI_IDDQ_MODE_0 _MK_ADDR_CONST(0xdc) +#define AFI_IDDQ_MODE_0_SECURE 0x0 +#define AFI_IDDQ_MODE_0_WORD_COUNT 0x1 +#define AFI_IDDQ_MODE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_0_RESET_MASK _MK_MASK_CONST(0x3) +#define AFI_IDDQ_MODE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_0_READ_MASK _MK_MASK_CONST(0x3) +#define AFI_IDDQ_MODE_0_WRITE_MASK _MK_MASK_CONST(0x3) +//SM (system management) to PCIE PLL assert IDDQ Mode +#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_FIELD (_MK_MASK_CONST(0x1) << AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_SHIFT) +#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_RANGE 0:0 +#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_WOFFSET 0x0 +#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) to PCIE PLL deassert IDDQ Mode +#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_SHIFT _MK_SHIFT_CONST(1) +#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_FIELD (_MK_MASK_CONST(0x1) << AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_SHIFT) +#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_RANGE 1:1 +#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_WOFFSET 0x0 +#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PLL_RESET_0 +#define AFI_PLL_RESET_0 _MK_ADDR_CONST(0xe0) +#define AFI_PLL_RESET_0_SECURE 0x0 +#define AFI_PLL_RESET_0_WORD_COUNT 0x1 +#define AFI_PLL_RESET_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_0_RESET_MASK _MK_MASK_CONST(0x3) +#define AFI_PLL_RESET_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_0_READ_MASK _MK_MASK_CONST(0x3) +#define AFI_PLL_RESET_0_WRITE_MASK _MK_MASK_CONST(0x3) +//SM (system management) to PCIE PLL assert Reset +#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_FIELD (_MK_MASK_CONST(0x1) << AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_SHIFT) +#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_RANGE 0:0 +#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_WOFFSET 0x0 +#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) to PCIE PLL deassert Reset +#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_SHIFT _MK_SHIFT_CONST(1) +#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_FIELD (_MK_MASK_CONST(0x1) << AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_SHIFT) +#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_RANGE 1:1 +#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_WOFFSET 0x0 +#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_IDDQ_MODE_ACK_0 +#define AFI_IDDQ_MODE_ACK_0 _MK_ADDR_CONST(0xe4) +#define AFI_IDDQ_MODE_ACK_0_SECURE 0x0 +#define AFI_IDDQ_MODE_ACK_0_WORD_COUNT 0x1 +#define AFI_IDDQ_MODE_ACK_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_ACK_0_RESET_MASK _MK_MASK_CONST(0x3) +#define AFI_IDDQ_MODE_ACK_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_ACK_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_ACK_0_READ_MASK _MK_MASK_CONST(0x3) +#define AFI_IDDQ_MODE_ACK_0_WRITE_MASK _MK_MASK_CONST(0x0) +//SM (system management) to PCIE PLL assert IDDQ Mode Ack +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_SHIFT _MK_SHIFT_CONST(0) +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_FIELD (_MK_MASK_CONST(0x1) << AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_SHIFT) +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_RANGE 0:0 +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_WOFFSET 0x0 +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) to PCIE PLL deassert IDDQ Mode Ack +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_SHIFT _MK_SHIFT_CONST(1) +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_FIELD (_MK_MASK_CONST(0x1) << AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_SHIFT) +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_RANGE 1:1 +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_WOFFSET 0x0 +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PLL_RESET_ACK_0 +#define AFI_PLL_RESET_ACK_0 _MK_ADDR_CONST(0xe8) +#define AFI_PLL_RESET_ACK_0_SECURE 0x0 +#define AFI_PLL_RESET_ACK_0_WORD_COUNT 0x1 +#define AFI_PLL_RESET_ACK_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_ACK_0_RESET_MASK _MK_MASK_CONST(0x3) +#define AFI_PLL_RESET_ACK_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_ACK_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_ACK_0_READ_MASK _MK_MASK_CONST(0x3) +#define AFI_PLL_RESET_ACK_0_WRITE_MASK _MK_MASK_CONST(0x0) +//SM (system management) to PCIE PLL assert Reset Ack +#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_FIELD (_MK_MASK_CONST(0x1) << AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_SHIFT) +#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_RANGE 0:0 +#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_WOFFSET 0x0 +#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) to PCIE PLL deassert Reset Ack +#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_SHIFT _MK_SHIFT_CONST(1) +#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_FIELD (_MK_MASK_CONST(0x1) << AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_SHIFT) +#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_RANGE 1:1 +#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_WOFFSET 0x0 +#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PCIE_THROTTLE_0 +#define AFI_PCIE_THROTTLE_0 _MK_ADDR_CONST(0xec) +#define AFI_PCIE_THROTTLE_0_SECURE 0x0 +#define AFI_PCIE_THROTTLE_0_WORD_COUNT 0x1 +#define AFI_PCIE_THROTTLE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_PCIE_THROTTLE_0_RESET_MASK _MK_MASK_CONST(0x8000fff7) +#define AFI_PCIE_THROTTLE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PCIE_THROTTLE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PCIE_THROTTLE_0_READ_MASK _MK_MASK_CONST(0x8000fff7) +#define AFI_PCIE_THROTTLE_0_WRITE_MASK _MK_MASK_CONST(0x8000fff7) +//Override THERM MGMT duty cycle +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_FIELD (_MK_MASK_CONST(0x7) << AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_SHIFT) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_RANGE 2:0 +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_WOFFSET 0x0 +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Override THERM MGMT period +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_SHIFT _MK_SHIFT_CONST(4) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_FIELD (_MK_MASK_CONST(0xfff) << AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_SHIFT) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_RANGE 15:4 +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_WOFFSET 0x0 +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_DEFAULT_MASK _MK_MASK_CONST(0xfff) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Override THERM MGMT +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_SHIFT _MK_SHIFT_CONST(31) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_SHIFT) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_RANGE 31:31 +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_WOFFSET 0x0 +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PME_0 +#define AFI_PME_0 _MK_ADDR_CONST(0xf0) +#define AFI_PME_0_SECURE 0x0 +#define AFI_PME_0_WORD_COUNT 0x1 +#define AFI_PME_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_PME_0_RESET_MASK _MK_MASK_CONST(0x1ff1) +#define AFI_PME_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PME_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PME_0_READ_MASK _MK_MASK_CONST(0x1ff1) +#define AFI_PME_0_WRITE_MASK _MK_MASK_CONST(0x101) +//SM (system management) to PCIE PME Turn Off +#define AFI_PME_0_SM2TMS0C0_PME_TO_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PME_0_SM2TMS0C0_PME_TO_FIELD (_MK_MASK_CONST(0x1) << AFI_PME_0_SM2TMS0C0_PME_TO_SHIFT) +#define AFI_PME_0_SM2TMS0C0_PME_TO_RANGE 0:0 +#define AFI_PME_0_SM2TMS0C0_PME_TO_WOFFSET 0x0 +#define AFI_PME_0_SM2TMS0C0_PME_TO_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_SM2TMS0C0_PME_TO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PME_0_SM2TMS0C0_PME_TO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_SM2TMS0C0_PME_TO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PCIE Endpoint PME message +#define AFI_PME_0_TMS0C02SM_PME_SHIFT _MK_SHIFT_CONST(4) +#define AFI_PME_0_TMS0C02SM_PME_FIELD (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C02SM_PME_SHIFT) +#define AFI_PME_0_TMS0C02SM_PME_RANGE 4:4 +#define AFI_PME_0_TMS0C02SM_PME_WOFFSET 0x0 +#define AFI_PME_0_TMS0C02SM_PME_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C02SM_PME_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PME_0_TMS0C02SM_PME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C02SM_PME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PCIE Endpoint PME Ack +#define AFI_PME_0_TMS0C02SM_PME_ACK_SHIFT _MK_SHIFT_CONST(5) +#define AFI_PME_0_TMS0C02SM_PME_ACK_FIELD (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C02SM_PME_ACK_SHIFT) +#define AFI_PME_0_TMS0C02SM_PME_ACK_RANGE 5:5 +#define AFI_PME_0_TMS0C02SM_PME_ACK_WOFFSET 0x0 +#define AFI_PME_0_TMS0C02SM_PME_ACK_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C02SM_PME_ACK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PME_0_TMS0C02SM_PME_ACK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C02SM_PME_ACK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PCIE Link Presence State +#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_SHIFT _MK_SHIFT_CONST(6) +#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_FIELD (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C02SM_PRESENCE_STATE_SHIFT) +#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_RANGE 6:6 +#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_WOFFSET 0x0 +#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//LTSSM ready for Power Down +#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_SHIFT _MK_SHIFT_CONST(7) +#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_FIELD (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_SHIFT) +#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_RANGE 7:7 +#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_WOFFSET 0x0 +#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) to PCIE PME Turn Off +#define AFI_PME_0_SM2TMS0C1_PME_TO_SHIFT _MK_SHIFT_CONST(8) +#define AFI_PME_0_SM2TMS0C1_PME_TO_FIELD (_MK_MASK_CONST(0x1) << AFI_PME_0_SM2TMS0C1_PME_TO_SHIFT) +#define AFI_PME_0_SM2TMS0C1_PME_TO_RANGE 8:8 +#define AFI_PME_0_SM2TMS0C1_PME_TO_WOFFSET 0x0 +#define AFI_PME_0_SM2TMS0C1_PME_TO_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_SM2TMS0C1_PME_TO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PME_0_SM2TMS0C1_PME_TO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_SM2TMS0C1_PME_TO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PCIE Endpoint PME message +#define AFI_PME_0_TMS0C12SM_PME_SHIFT _MK_SHIFT_CONST(9) +#define AFI_PME_0_TMS0C12SM_PME_FIELD (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C12SM_PME_SHIFT) +#define AFI_PME_0_TMS0C12SM_PME_RANGE 9:9 +#define AFI_PME_0_TMS0C12SM_PME_WOFFSET 0x0 +#define AFI_PME_0_TMS0C12SM_PME_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C12SM_PME_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PME_0_TMS0C12SM_PME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C12SM_PME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PCIE Endpoint PME Ack +#define AFI_PME_0_TMS0C12SM_PME_ACK_SHIFT _MK_SHIFT_CONST(10) +#define AFI_PME_0_TMS0C12SM_PME_ACK_FIELD (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C12SM_PME_ACK_SHIFT) +#define AFI_PME_0_TMS0C12SM_PME_ACK_RANGE 10:10 +#define AFI_PME_0_TMS0C12SM_PME_ACK_WOFFSET 0x0 +#define AFI_PME_0_TMS0C12SM_PME_ACK_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C12SM_PME_ACK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PME_0_TMS0C12SM_PME_ACK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C12SM_PME_ACK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PCIE Link Presence State +#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_SHIFT _MK_SHIFT_CONST(11) +#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_FIELD (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C12SM_PRESENCE_STATE_SHIFT) +#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_RANGE 11:11 +#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_WOFFSET 0x0 +#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//LTSSM ready for Power Down +#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_SHIFT _MK_SHIFT_CONST(12) +#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_FIELD (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_SHIFT) +#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_RANGE 12:12 +#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_WOFFSET 0x0 +#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_REQ_PENDING_0 +#define AFI_REQ_PENDING_0 _MK_ADDR_CONST(0xf4) +#define AFI_REQ_PENDING_0_SECURE 0x0 +#define AFI_REQ_PENDING_0_WORD_COUNT 0x1 +#define AFI_REQ_PENDING_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_RESET_MASK _MK_MASK_CONST(0xff) +#define AFI_REQ_PENDING_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_READ_MASK _MK_MASK_CONST(0xff) +#define AFI_REQ_PENDING_0_WRITE_MASK _MK_MASK_CONST(0x0) +//SM (system management) status that coherent request pending +//from PCIE to FPCI +#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_SHIFT _MK_SHIFT_CONST(0) +#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_FIELD (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_SHIFT) +#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_RANGE 0:0 +#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_WOFFSET 0x0 +#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) status that Non-coherent request pending +//from PCIE to FPCI +#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_SHIFT _MK_SHIFT_CONST(1) +#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_FIELD (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_SHIFT) +#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_RANGE 1:1 +#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_WOFFSET 0x0 +#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) status that ISO request pending +//from PCIE to FPCI +#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_SHIFT _MK_SHIFT_CONST(2) +#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_FIELD (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_SHIFT) +#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_RANGE 2:2 +#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_WOFFSET 0x0 +#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) status that Non-ISO request pending +//from PCIE to FPCI +#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_SHIFT _MK_SHIFT_CONST(3) +#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_FIELD (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_SHIFT) +#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_RANGE 3:3 +#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_WOFFSET 0x0 +#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) status that coherent request pending +//from PCIE to FPCI +#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_SHIFT _MK_SHIFT_CONST(4) +#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_FIELD (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_SHIFT) +#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_RANGE 4:4 +#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_WOFFSET 0x0 +#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) status that Non-coherent request pending +//from PCIE to FPCI +#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_SHIFT _MK_SHIFT_CONST(5) +#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_FIELD (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_SHIFT) +#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_RANGE 5:5 +#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_WOFFSET 0x0 +#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) status that ISO request pending +//from PCIE to FPCI +#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_SHIFT _MK_SHIFT_CONST(6) +#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_FIELD (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_SHIFT) +#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_RANGE 6:6 +#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_WOFFSET 0x0 +#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) status that Non-ISO request pending +//from PCIE to FPCI +#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_SHIFT _MK_SHIFT_CONST(7) +#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_FIELD (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_SHIFT) +#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_RANGE 7:7 +#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_WOFFSET 0x0 +#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PCIE_CONFIG_0 +#define AFI_PCIE_CONFIG_0 _MK_ADDR_CONST(0xf8) +#define AFI_PCIE_CONFIG_0_SECURE 0x0 +#define AFI_PCIE_CONFIG_0_WORD_COUNT 0x1 +#define AFI_PCIE_CONFIG_0_RESET_VAL _MK_MASK_CONST(0x3024) +#define AFI_PCIE_CONFIG_0_RESET_MASK _MK_MASK_CONST(0xf1f1f7) +#define AFI_PCIE_CONFIG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_READ_MASK _MK_MASK_CONST(0xf1f1f7) +#define AFI_PCIE_CONFIG_0_WRITE_MASK _MK_MASK_CONST(0xf1f1f7) +//CYA to indicate PCIE slot empty. Overrides PCIE slot present input. +#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_SHIFT) +#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_RANGE 0:0 +#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_WOFFSET 0x0 +#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Disable PCIE Controller 0 (default off) +#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_SHIFT _MK_SHIFT_CONST(1) +#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_SHIFT) +#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_RANGE 1:1 +#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_WOFFSET 0x0 +#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Disable PCIE Controller 1 (default on) +#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_SHIFT _MK_SHIFT_CONST(2) +#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_SHIFT) +#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_RANGE 2:2 +#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_WOFFSET 0x0 +#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//T0C0 Upstream FPCI Unit ID. HyperTransport, upstream FPCI request +#define AFI_PCIE_CONFIG_0_UNITID_T0C0_SHIFT _MK_SHIFT_CONST(4) +#define AFI_PCIE_CONFIG_0_UNITID_T0C0_FIELD (_MK_MASK_CONST(0x1f) << AFI_PCIE_CONFIG_0_UNITID_T0C0_SHIFT) +#define AFI_PCIE_CONFIG_0_UNITID_T0C0_RANGE 8:4 +#define AFI_PCIE_CONFIG_0_UNITID_T0C0_WOFFSET 0x0 +#define AFI_PCIE_CONFIG_0_UNITID_T0C0_DEFAULT _MK_MASK_CONST(0x2) +#define AFI_PCIE_CONFIG_0_UNITID_T0C0_DEFAULT_MASK _MK_MASK_CONST(0x1f) +#define AFI_PCIE_CONFIG_0_UNITID_T0C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_UNITID_T0C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//T0C1 Upstream FPCI Unit ID. HyperTransport, upstream FPCI request +//Downstream FPCI unit ID should remain 0. +#define AFI_PCIE_CONFIG_0_UNITID_T0C1_SHIFT _MK_SHIFT_CONST(12) +#define AFI_PCIE_CONFIG_0_UNITID_T0C1_FIELD (_MK_MASK_CONST(0x1f) << AFI_PCIE_CONFIG_0_UNITID_T0C1_SHIFT) +#define AFI_PCIE_CONFIG_0_UNITID_T0C1_RANGE 16:12 +#define AFI_PCIE_CONFIG_0_UNITID_T0C1_WOFFSET 0x0 +#define AFI_PCIE_CONFIG_0_UNITID_T0C1_DEFAULT _MK_MASK_CONST(0x3) +#define AFI_PCIE_CONFIG_0_UNITID_T0C1_DEFAULT_MASK _MK_MASK_CONST(0x1f) +#define AFI_PCIE_CONFIG_0_UNITID_T0C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_UNITID_T0C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//SM (system management) configuration of PCIE crossbar. +//There are 2 possible configurations for PCIE crossbar: +// 0 : Single controller - T0C0 4 lanes +// 1 : Dual controller - T0C0 2 lanes/T0C1 2 lanes +#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_SHIFT _MK_SHIFT_CONST(20) +#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_FIELD (_MK_MASK_CONST(0xf) << AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_SHIFT) +#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_RANGE 23:20 +#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_WOFFSET 0x0 +#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_REV_ID_0 +#define AFI_REV_ID_0 _MK_ADDR_CONST(0xfc) +#define AFI_REV_ID_0_SECURE 0x0 +#define AFI_REV_ID_0_WORD_COUNT 0x1 +#define AFI_REV_ID_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_REV_ID_0_RESET_MASK _MK_MASK_CONST(0x3) +#define AFI_REV_ID_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_REV_ID_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_REV_ID_0_READ_MASK _MK_MASK_CONST(0x3) +#define AFI_REV_ID_0_WRITE_MASK _MK_MASK_CONST(0x3) +//Override for PCI config revision id read-only register. +//This allows backdoor changes to rev ID for metal spins. +#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_SHIFT _MK_SHIFT_CONST(0) +#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_FIELD (_MK_MASK_CONST(0x1) << AFI_REV_ID_0_CFG_REVID_OVERRIDE_SHIFT) +#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_RANGE 0:0 +#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_WOFFSET 0x0 +#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Write Enable for PCI backdoor rev ID override value. +#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_SHIFT _MK_SHIFT_CONST(1) +#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_FIELD (_MK_MASK_CONST(0x1) << AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_SHIFT) +#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_RANGE 1:1 +#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_WOFFSET 0x0 +#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_TOM_0 +#define AFI_TOM_0 _MK_ADDR_CONST(0x100) +#define AFI_TOM_0_SECURE 0x0 +#define AFI_TOM_0_WORD_COUNT 0x1 +#define AFI_TOM_0_RESET_VAL _MK_MASK_CONST(0x3f3f003f) +#define AFI_TOM_0_RESET_MASK _MK_MASK_CONST(0x3fff003f) +#define AFI_TOM_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_TOM_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_TOM_0_READ_MASK _MK_MASK_CONST(0x3fff003f) +#define AFI_TOM_0_WRITE_MASK _MK_MASK_CONST(0x3fff003f) +//Top of Memory Limit 1. Determines peer-to-peer range as: +//{TOM1 :: 26'b0} to 0xFFFF_FFFF (except MSI region) +#define AFI_TOM_0_DLDT2ALL_TOM1_SHIFT _MK_SHIFT_CONST(0) +#define AFI_TOM_0_DLDT2ALL_TOM1_FIELD (_MK_MASK_CONST(0x3f) << AFI_TOM_0_DLDT2ALL_TOM1_SHIFT) +#define AFI_TOM_0_DLDT2ALL_TOM1_RANGE 5:0 +#define AFI_TOM_0_DLDT2ALL_TOM1_WOFFSET 0x0 +#define AFI_TOM_0_DLDT2ALL_TOM1_DEFAULT _MK_MASK_CONST(0x3f) +#define AFI_TOM_0_DLDT2ALL_TOM1_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define AFI_TOM_0_DLDT2ALL_TOM1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_TOM_0_DLDT2ALL_TOM1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Top of Memory Limit 2. Determines peer-to-peer range as: +//{TOM2 :: 26'b0} to 0xFC_FFFF_FFFF +#define AFI_TOM_0_DLDT2ALL_TOM2_SHIFT _MK_SHIFT_CONST(16) +#define AFI_TOM_0_DLDT2ALL_TOM2_FIELD (_MK_MASK_CONST(0x3fff) << AFI_TOM_0_DLDT2ALL_TOM2_SHIFT) +#define AFI_TOM_0_DLDT2ALL_TOM2_RANGE 29:16 +#define AFI_TOM_0_DLDT2ALL_TOM2_WOFFSET 0x0 +#define AFI_TOM_0_DLDT2ALL_TOM2_DEFAULT _MK_MASK_CONST(0x3f3f) +#define AFI_TOM_0_DLDT2ALL_TOM2_DEFAULT_MASK _MK_MASK_CONST(0x3fff) +#define AFI_TOM_0_DLDT2ALL_TOM2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_TOM_0_DLDT2ALL_TOM2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_FUSE_0 +#define AFI_FUSE_0 _MK_ADDR_CONST(0x104) +#define AFI_FUSE_0_SECURE 0x0 +#define AFI_FUSE_0_WORD_COUNT 0x1 +#define AFI_FUSE_0_RESET_VAL _MK_MASK_CONST(0x336) +#define AFI_FUSE_0_RESET_MASK _MK_MASK_CONST(0x777) +#define AFI_FUSE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_FUSE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_FUSE_0_READ_MASK _MK_MASK_CONST(0x777) +#define AFI_FUSE_0_WRITE_MASK _MK_MASK_CONST(0x777) +//Enable advanced error reporting capability of PCIE. +//This should remain off for AP20. +#define AFI_FUSE_0_FUSE_PCIE_AER_EN_SHIFT _MK_SHIFT_CONST(0) +#define AFI_FUSE_0_FUSE_PCIE_AER_EN_FIELD (_MK_MASK_CONST(0x1) << AFI_FUSE_0_FUSE_PCIE_AER_EN_SHIFT) +#define AFI_FUSE_0_FUSE_PCIE_AER_EN_RANGE 0:0 +#define AFI_FUSE_0_FUSE_PCIE_AER_EN_WOFFSET 0x0 +#define AFI_FUSE_0_FUSE_PCIE_AER_EN_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FUSE_0_FUSE_PCIE_AER_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FUSE_0_FUSE_PCIE_AER_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FUSE_0_FUSE_PCIE_AER_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Disable SLI capability for GPU. This should remain on for AP20. +#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_SHIFT _MK_SHIFT_CONST(1) +#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_FIELD (_MK_MASK_CONST(0x1) << AFI_FUSE_0_FUSE_PCIE_SLI_DIS_SHIFT) +#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_RANGE 1:1 +#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_WOFFSET 0x0 +#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Disable Gen 2 capability of PCIE. This should remain on for AP20. +#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_SHIFT _MK_SHIFT_CONST(2) +#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_FIELD (_MK_MASK_CONST(0x1) << AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_SHIFT) +#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_RANGE 2:2 +#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_WOFFSET 0x0 +#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Configure PCIE as x1, x2, x4, x8, or x16. +//This should remain 3'b011 for AP20 +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_SHIFT _MK_SHIFT_CONST(4) +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_FIELD (_MK_MASK_CONST(0x7) << AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_SHIFT) +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_RANGE 6:4 +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_WOFFSET 0x0 +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_DEFAULT _MK_MASK_CONST(0x3) +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Configure PCIE as x1, x2, x4, x8, or x16. +//This should remain 3'b011 for AP20 +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_SHIFT _MK_SHIFT_CONST(8) +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_FIELD (_MK_MASK_CONST(0x7) << AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_SHIFT) +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_RANGE 10:8 +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_WOFFSET 0x0 +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_DEFAULT _MK_MASK_CONST(0x3) +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PMU_0 +#define AFI_PMU_0 _MK_ADDR_CONST(0x108) +#define AFI_PMU_0_SECURE 0x0 +#define AFI_PMU_0_WORD_COUNT 0x1 +#define AFI_PMU_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_PMU_0_RESET_MASK _MK_MASK_CONST(0x1f1fff1) +#define AFI_PMU_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PMU_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PMU_0_READ_MASK _MK_MASK_CONST(0x1f1fff1) +#define AFI_PMU_0_WRITE_MASK _MK_MASK_CONST(0xff1) +//PMU Load Indicator Enable. +//This is used for wall-plug applications and should remain off for AP20. +#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_FIELD (_MK_MASK_CONST(0x1) << AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_SHIFT) +#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_RANGE 0:0 +#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_WOFFSET 0x0 +#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PMU Load Indicator Scale for T0C0 +#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_SHIFT _MK_SHIFT_CONST(4) +#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_FIELD (_MK_MASK_CONST(0xf) << AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_SHIFT) +#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_RANGE 7:4 +#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_WOFFSET 0x0 +#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PMU Load Indicator Scale for T0C1 +#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_SHIFT _MK_SHIFT_CONST(8) +#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_FIELD (_MK_MASK_CONST(0xf) << AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_SHIFT) +#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_RANGE 11:8 +#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_WOFFSET 0x0 +#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PMU Status +#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_SHIFT _MK_SHIFT_CONST(12) +#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_FIELD (_MK_MASK_CONST(0xf) << AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_SHIFT) +#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_RANGE 15:12 +#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_WOFFSET 0x0 +#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PMU toggle response from PCIE +#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_SHIFT _MK_SHIFT_CONST(16) +#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_FIELD (_MK_MASK_CONST(0x1) << AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_SHIFT) +#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_RANGE 16:16 +#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_WOFFSET 0x0 +#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PMU Status +#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_SHIFT _MK_SHIFT_CONST(20) +#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_FIELD (_MK_MASK_CONST(0xf) << AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_SHIFT) +#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_RANGE 23:20 +#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_WOFFSET 0x0 +#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PMU toggle response from PCIE +#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_SHIFT _MK_SHIFT_CONST(24) +#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_FIELD (_MK_MASK_CONST(0x1) << AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_SHIFT) +#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_RANGE 24:24 +#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_WOFFSET 0x0 +#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PCIE_CLK_CONFIG_STATUS_0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0 _MK_ADDR_CONST(0x10c) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_SECURE 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_WORD_COUNT 0x1 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_RESET_MASK _MK_MASK_CONST(0xff3f1f) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_READ_MASK _MK_MASK_CONST(0xff3f1f) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x1f) +//Acknowledge to Select XCLK Gen2 request. +//This should remain low for AP20. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_RANGE 0:0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Acknowledge to Select T0C0 XTXCLK1X Gen2 request. +//This should remain low for AP20. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_SHIFT _MK_SHIFT_CONST(1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_RANGE 1:1 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Acknowledge to Disable T0C0 XTXCLK1X request. Used for clock gating. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_SHIFT _MK_SHIFT_CONST(2) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_RANGE 2:2 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Acknowledge to Select T0C0 XTXCLK1X Gen2 request. +//This should remain low for AP20. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_SHIFT _MK_SHIFT_CONST(3) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_RANGE 3:3 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Acknowledge to Disable T0C0 XTXCLK1X request. Used for clock gating. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_SHIFT _MK_SHIFT_CONST(4) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_RANGE 4:4 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Request to select Gen2 speed clock (500 MHz) for XCLK. +//This is generated when register settings for PCIE2 specify +//Gen2 speed clocks. This should remain low for AP20. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_SHIFT _MK_SHIFT_CONST(8) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_RANGE 8:8 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Request to select Gen2 speed clock (500 MHz) for T0C0 XTXCLK1X. +//This is generated when register settings for PCIE2 specify +//Gen2 speed clocks. This should remain low for AP20. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_SHIFT _MK_SHIFT_CONST(9) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_RANGE 9:9 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Request to select Gen2 speed clock (500 MHz) for T0C1 XTXCLK1X. +//This is generated when register settings for PCIE2 specify +//Gen2 speed clocks. This should remain low for AP20. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_SHIFT _MK_SHIFT_CONST(10) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_RANGE 10:10 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Request to gate TMS/FPCI clocks when in low power mode. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_SHIFT _MK_SHIFT_CONST(11) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_RANGE 11:11 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Request to gate T0C0 XTXCLK1X when in low power mode. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_SHIFT _MK_SHIFT_CONST(12) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_RANGE 12:12 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Request to gate T0C1 XTXCLK1X when in low power mode. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_SHIFT _MK_SHIFT_CONST(13) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_FIELD (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_RANGE 13:13 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Clock select to pad macro. For AP20, this should remain 0. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_SHIFT _MK_SHIFT_CONST(16) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_FIELD (_MK_MASK_CONST(0xf) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_RANGE 19:16 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//Clock select to pad macro. For AP20, this should remain 0. +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_SHIFT _MK_SHIFT_CONST(20) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_FIELD (_MK_MASK_CONST(0xf) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_SHIFT) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_RANGE 23:20 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_WOFFSET 0x0 +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PEX0_CTRL_0 +#define AFI_PEX0_CTRL_0 _MK_ADDR_CONST(0x110) +#define AFI_PEX0_CTRL_0_SECURE 0x0 +#define AFI_PEX0_CTRL_0_WORD_COUNT 0x1 +#define AFI_PEX0_CTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_PEX0_CTRL_0_RESET_MASK _MK_MASK_CONST(0x89) +#define AFI_PEX0_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PEX0_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PEX0_CTRL_0_READ_MASK _MK_MASK_CONST(0x89) +#define AFI_PEX0_CTRL_0_WRITE_MASK _MK_MASK_CONST(0x89) +//PEX0 external pe0_rst_l register +#define AFI_PEX0_CTRL_0_PEX0_RST_L_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PEX0_CTRL_0_PEX0_RST_L_FIELD (_MK_MASK_CONST(0x1) << AFI_PEX0_CTRL_0_PEX0_RST_L_SHIFT) +#define AFI_PEX0_CTRL_0_PEX0_RST_L_RANGE 0:0 +#define AFI_PEX0_CTRL_0_PEX0_RST_L_WOFFSET 0x0 +#define AFI_PEX0_CTRL_0_PEX0_RST_L_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX0_CTRL_0_PEX0_RST_L_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX0_CTRL_0_PEX0_RST_L_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX0_CTRL_0_PEX0_RST_L_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PEX0 enable to clkout pad +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_SHIFT _MK_SHIFT_CONST(3) +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_FIELD (_MK_MASK_CONST(0x1) << AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_SHIFT) +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_RANGE 3:3 +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_WOFFSET 0x0 +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PEX0 refclk select 0=PLLE, 1=PHY REFCLK +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_SHIFT _MK_SHIFT_CONST(7) +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_FIELD (_MK_MASK_CONST(0x1) << AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_SHIFT) +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_RANGE 7:7 +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_WOFFSET 0x0 +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PEX0_STATUS_0 +#define AFI_PEX0_STATUS_0 _MK_ADDR_CONST(0x114) +#define AFI_PEX0_STATUS_0_SECURE 0x0 +#define AFI_PEX0_STATUS_0_WORD_COUNT 0x1 +#define AFI_PEX0_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_PEX0_STATUS_0_RESET_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX0_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PEX0_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PEX0_STATUS_0_READ_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX0_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x0) +//status PEX0 pe0_clkreq_l input +#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_FIELD (_MK_MASK_CONST(0x1) << AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_SHIFT) +#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_RANGE 0:0 +#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_WOFFSET 0x0 +#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PEX1_CTRL_0 +#define AFI_PEX1_CTRL_0 _MK_ADDR_CONST(0x118) +#define AFI_PEX1_CTRL_0_SECURE 0x0 +#define AFI_PEX1_CTRL_0_WORD_COUNT 0x1 +#define AFI_PEX1_CTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_PEX1_CTRL_0_RESET_MASK _MK_MASK_CONST(0x89) +#define AFI_PEX1_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PEX1_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PEX1_CTRL_0_READ_MASK _MK_MASK_CONST(0x89) +#define AFI_PEX1_CTRL_0_WRITE_MASK _MK_MASK_CONST(0x89) +//PEX1 external pe1_rst_l register +#define AFI_PEX1_CTRL_0_PEX1_RST_L_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PEX1_CTRL_0_PEX1_RST_L_FIELD (_MK_MASK_CONST(0x1) << AFI_PEX1_CTRL_0_PEX1_RST_L_SHIFT) +#define AFI_PEX1_CTRL_0_PEX1_RST_L_RANGE 0:0 +#define AFI_PEX1_CTRL_0_PEX1_RST_L_WOFFSET 0x0 +#define AFI_PEX1_CTRL_0_PEX1_RST_L_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX1_CTRL_0_PEX1_RST_L_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX1_CTRL_0_PEX1_RST_L_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX1_CTRL_0_PEX1_RST_L_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PEX1 enable to clkout pad +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_SHIFT _MK_SHIFT_CONST(3) +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_FIELD (_MK_MASK_CONST(0x1) << AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_SHIFT) +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_RANGE 3:3 +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_WOFFSET 0x0 +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +//PEX1 refclk select 0=PLLE, 1=PHY REFCLK +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_SHIFT _MK_SHIFT_CONST(7) +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_FIELD (_MK_MASK_CONST(0x1) << AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_SHIFT) +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_RANGE 7:7 +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_WOFFSET 0x0 +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_PEX1_STATUS_0 +#define AFI_PEX1_STATUS_0 _MK_ADDR_CONST(0x11c) +#define AFI_PEX1_STATUS_0_SECURE 0x0 +#define AFI_PEX1_STATUS_0_WORD_COUNT 0x1 +#define AFI_PEX1_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_PEX1_STATUS_0_RESET_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX1_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_PEX1_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_PEX1_STATUS_0_READ_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX1_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x0) +//status PEX1 pe1_clkreq_l input +#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_SHIFT _MK_SHIFT_CONST(0) +#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_FIELD (_MK_MASK_CONST(0x1) << AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_SHIFT) +#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_RANGE 0:0 +#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_WOFFSET 0x0 +#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_WR_SCRATCH_0 +#define AFI_WR_SCRATCH_0 _MK_ADDR_CONST(0x120) +#define AFI_WR_SCRATCH_0_SECURE 0x0 +#define AFI_WR_SCRATCH_0_WORD_COUNT 0x1 +#define AFI_WR_SCRATCH_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_WR_SCRATCH_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_WR_SCRATCH_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_WR_SCRATCH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_WR_SCRATCH_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_WR_SCRATCH_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +//Scratch registers to write +#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_SHIFT _MK_SHIFT_CONST(0) +#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_SHIFT) +#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_RANGE 31:0 +#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_WOFFSET 0x0 +#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_RD_SCRATCH_0 +#define AFI_RD_SCRATCH_0 _MK_ADDR_CONST(0x124) +#define AFI_RD_SCRATCH_0_SECURE 0x0 +#define AFI_RD_SCRATCH_0_WORD_COUNT 0x1 +#define AFI_RD_SCRATCH_0_RESET_VAL _MK_MASK_CONST(0x0) +#define AFI_RD_SCRATCH_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_RD_SCRATCH_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_RD_SCRATCH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_RD_SCRATCH_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_RD_SCRATCH_0_WRITE_MASK _MK_MASK_CONST(0x0) +//Scratch registers to read +#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_SHIFT _MK_SHIFT_CONST(0) +#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_FIELD (_MK_MASK_CONST(0xffffffff) << AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_SHIFT) +#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_RANGE 31:0 +#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_WOFFSET 0x0 +#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register AFI_DUMMY_REG_0 +#define AFI_DUMMY_REG_0 _MK_ADDR_CONST(0x128) +#define AFI_DUMMY_REG_0_SECURE 0x0 +#define AFI_DUMMY_REG_0_WORD_COUNT 0x1 +#define AFI_DUMMY_REG_0_RESET_VAL _MK_MASK_CONST(0x1) +#define AFI_DUMMY_REG_0_RESET_MASK _MK_MASK_CONST(0x1) +#define AFI_DUMMY_REG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define AFI_DUMMY_REG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define AFI_DUMMY_REG_0_READ_MASK _MK_MASK_CONST(0x1) +#define AFI_DUMMY_REG_0_WRITE_MASK _MK_MASK_CONST(0x1) +//Dummy register +#define AFI_DUMMY_REG_0_DUMMY_SHIFT _MK_SHIFT_CONST(0) +#define AFI_DUMMY_REG_0_DUMMY_FIELD (_MK_MASK_CONST(0x1) << AFI_DUMMY_REG_0_DUMMY_SHIFT) +#define AFI_DUMMY_REG_0_DUMMY_RANGE 0:0 +#define AFI_DUMMY_REG_0_DUMMY_WOFFSET 0x0 +#define AFI_DUMMY_REG_0_DUMMY_DEFAULT _MK_MASK_CONST(0x1) +#define AFI_DUMMY_REG_0_DUMMY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define AFI_DUMMY_REG_0_DUMMY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define AFI_DUMMY_REG_0_DUMMY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Packet PCIE_INTINFO_ADDR +#define PCIE_INTINFO_ADDR_SIZE 30 + +//When interrupt code is not equal to 6, the INT_INFO field of the +//interrupt signature register contains either the AXI or FPCI address +//bits[31:2] of the read or write transaction causing the interrupt +#define PCIE_INTINFO_ADDR_INTERRUPT_ADDRESS_SHIFT _MK_SHIFT_CONST(2) +#define PCIE_INTINFO_ADDR_INTERRUPT_ADDRESS_FIELD (_MK_MASK_CONST(0x3fffffff) << PCIE_INTINFO_ADDR_INTERRUPT_ADDRESS_SHIFT) +#define PCIE_INTINFO_ADDR_INTERRUPT_ADDRESS_RANGE _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(2) +#define PCIE_INTINFO_ADDR_INTERRUPT_ADDRESS_ROW 0 + + +// Packet PCIE_INTINFO_SM +#define PCIE_INTINFO_SM_SIZE 13 + +//Unit ID of the PCIE2 controller generating the system management message. +//This will correspond to UNITID_T0C0 or UNITID_T0C1 of PCIE_CONFIG register. +#define PCIE_INTINFO_SM_SM_UNIT_ID_SHIFT _MK_SHIFT_CONST(10) +#define PCIE_INTINFO_SM_SM_UNIT_ID_FIELD (_MK_MASK_CONST(0x1f) << PCIE_INTINFO_SM_SM_UNIT_ID_SHIFT) +#define PCIE_INTINFO_SM_SM_UNIT_ID_RANGE _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(10) +#define PCIE_INTINFO_SM_SM_UNIT_ID_ROW 0 + +//System management message +#define PCIE_INTINFO_SM_SM_MESSAGE_SHIFT _MK_SHIFT_CONST(2) +#define PCIE_INTINFO_SM_SM_MESSAGE_FIELD (_MK_MASK_CONST(0x1f) << PCIE_INTINFO_SM_SM_MESSAGE_SHIFT) +#define PCIE_INTINFO_SM_SM_MESSAGE_RANGE _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(2) +#define PCIE_INTINFO_SM_SM_MESSAGE_ROW 0 +#define PCIE_INTINFO_SM_SM_MESSAGE_INTA_ASSERT _MK_ENUM_CONST(16) // //Interrupt A Assertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_INTB_ASSERT _MK_ENUM_CONST(20) // //Interrupt B Assertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_INTC_ASSERT _MK_ENUM_CONST(24) // //Interrupt C Assertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_INTD_ASSERT _MK_ENUM_CONST(28) // //Interrupt D Assertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_INTA_DEASSERT _MK_ENUM_CONST(0) // //Interrupt A Deassertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_INTB_DEASSERT _MK_ENUM_CONST(4) // //Interrupt B Deassertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_INTC_DEASSERT _MK_ENUM_CONST(8) // //Interrupt C Deassertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_INTD_DEASSERT _MK_ENUM_CONST(12) // //Interrupt D Deassertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_ERR_CORRECTABLE _MK_ENUM_CONST(1) // //Correctable Error + +#define PCIE_INTINFO_SM_SM_MESSAGE_ERR_UNCORRECTABLE_NONFATAL _MK_ENUM_CONST(5) // //Un-Correctable Non-Fatal Error + +#define PCIE_INTINFO_SM_SM_MESSAGE_ERR_UNCORRECTABLE_FATAL _MK_ENUM_CONST(9) // //Un-Correctable Fatal Error + +#define PCIE_INTINFO_SM_SM_MESSAGE_PME_ASSERT _MK_ENUM_CONST(2) // //PME Assertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_HOTPLUG_ASSERT _MK_ENUM_CONST(6) // //Hotplug Assertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_RP_ASSERT _MK_ENUM_CONST(19) // //Root Port Assertion + +#define PCIE_INTINFO_SM_SM_MESSAGE_RP_DEASSERT _MK_ENUM_CONST(3) // //Root Port Deassertion + + + +// +// REGISTER LIST +// +#define LIST_ARAFI_REGS(_op_) \ +_op_(AFI_AXI_BAR0_SZ_0) \ +_op_(AFI_AXI_BAR1_SZ_0) \ +_op_(AFI_AXI_BAR2_SZ_0) \ +_op_(AFI_AXI_BAR3_SZ_0) \ +_op_(AFI_AXI_BAR4_SZ_0) \ +_op_(AFI_AXI_BAR5_SZ_0) \ +_op_(AFI_AXI_BAR0_START_0) \ +_op_(AFI_AXI_BAR1_START_0) \ +_op_(AFI_AXI_BAR2_START_0) \ +_op_(AFI_AXI_BAR3_START_0) \ +_op_(AFI_AXI_BAR4_START_0) \ +_op_(AFI_AXI_BAR5_START_0) \ +_op_(AFI_FPCI_BAR0_0) \ +_op_(AFI_FPCI_BAR1_0) \ +_op_(AFI_FPCI_BAR2_0) \ +_op_(AFI_FPCI_BAR3_0) \ +_op_(AFI_FPCI_BAR4_0) \ +_op_(AFI_FPCI_BAR5_0) \ +_op_(AFI_CACHE_BAR0_SZ_0) \ +_op_(AFI_CACHE_BAR0_ST_0) \ +_op_(AFI_CACHE_BAR1_SZ_0) \ +_op_(AFI_CACHE_BAR1_ST_0) \ +_op_(AFI_IO_BAR_SZ_0) \ +_op_(AFI_IO_BAR_ST_0) \ +_op_(AFI_MSI_BAR_SZ_0) \ +_op_(AFI_MSI_FPCI_BAR_ST_0) \ +_op_(AFI_MSI_AXI_BAR_ST_0) \ +_op_(AFI_MSI_VEC0_0) \ +_op_(AFI_MSI_VEC1_0) \ +_op_(AFI_MSI_VEC2_0) \ +_op_(AFI_MSI_VEC3_0) \ +_op_(AFI_MSI_VEC4_0) \ +_op_(AFI_MSI_VEC5_0) \ +_op_(AFI_MSI_VEC6_0) \ +_op_(AFI_MSI_VEC7_0) \ +_op_(AFI_MSI_EN_VEC0_0) \ +_op_(AFI_MSI_EN_VEC1_0) \ +_op_(AFI_MSI_EN_VEC2_0) \ +_op_(AFI_MSI_EN_VEC3_0) \ +_op_(AFI_MSI_EN_VEC4_0) \ +_op_(AFI_MSI_EN_VEC5_0) \ +_op_(AFI_MSI_EN_VEC6_0) \ +_op_(AFI_MSI_EN_VEC7_0) \ +_op_(AFI_CONFIGURATION_0) \ +_op_(AFI_FPCI_ERROR_MASKS_0) \ +_op_(AFI_INTR_MASK_0) \ +_op_(AFI_INTR_CODE_0) \ +_op_(AFI_INTR_SIGNATURE_0) \ +_op_(AFI_UPPER_FPCI_ADDR_0) \ +_op_(AFI_SM_INTR_ENABLE_0) \ +_op_(AFI_AFI_INTR_ENABLE_0) \ +_op_(AFI_AUSER_OVERRIDE_0) \ +_op_(AFI_ACACHE_OVERRIDE_0) \ +_op_(AFI_APROT_OVERRIDE_0) \ +_op_(AFI_FPCI_TIMEOUT_0) \ +_op_(AFI_IDDQ_MODE_0) \ +_op_(AFI_PLL_RESET_0) \ +_op_(AFI_IDDQ_MODE_ACK_0) \ +_op_(AFI_PLL_RESET_ACK_0) \ +_op_(AFI_PCIE_THROTTLE_0) \ +_op_(AFI_PME_0) \ +_op_(AFI_REQ_PENDING_0) \ +_op_(AFI_PCIE_CONFIG_0) \ +_op_(AFI_REV_ID_0) \ +_op_(AFI_TOM_0) \ +_op_(AFI_FUSE_0) \ +_op_(AFI_PMU_0) \ +_op_(AFI_PCIE_CLK_CONFIG_STATUS_0) \ +_op_(AFI_PEX0_CTRL_0) \ +_op_(AFI_PEX0_STATUS_0) \ +_op_(AFI_PEX1_CTRL_0) \ +_op_(AFI_PEX1_STATUS_0) \ +_op_(AFI_WR_SCRATCH_0) \ +_op_(AFI_RD_SCRATCH_0) \ +_op_(AFI_DUMMY_REG_0) + + +// +// ADDRESS SPACES +// + +#define BASE_ADDRESS_AFI 0x00000000 + +// +// ARAFI REGISTER BANKS +// + +#define AFI0_FIRST_REG 0x0000 // AFI_AXI_BAR0_SZ_0 +#define AFI0_LAST_REG 0x0128 // AFI_DUMMY_REG_0 + +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif + +#endif // ifndef ___ARAFI_H_INC_ diff --git a/arch/arm/mach-tegra/include/ap20/dev_ap_pcie2_pads.h b/arch/arm/mach-tegra/include/ap20/dev_ap_pcie2_pads.h new file mode 100644 index 000000000000..d0a4907e72c6 --- /dev/null +++ b/arch/arm/mach-tegra/include/ap20/dev_ap_pcie2_pads.h @@ -0,0 +1,466 @@ +/* + * Copyright (c) 2009 NVIDIA Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the NVIDIA Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef ___DEV_AP_PCIE2_PADS_H_INC_ +#define ___DEV_AP_PCIE2_PADS_H_INC_ + +#define NV_PROJ__PCIE2_PADS 0x000000BC:0x00000098 /* RW--D */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_0 0x00000098 /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT 31:0 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_DEFAULT 0xFFFFFFFF /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_NO_LANES 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_LANES_31_0 0xFFFFFFFF /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_MASK 0x0000001C /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_1 0x0000009C /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT 31:0 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT_DEFAULT 0xFFFFFFFF /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT_NO_LANES 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT_LANES_63_32 0xFFFFFFFF /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1 0x000000A0 /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_CTL_1_IDDQ_1L 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_IDDQ_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P_PD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P_NOT_PD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P 3:3 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L 5:4 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_DEFAULT 0x00000003 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_ACTIVE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_PARTIAL 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_SLUMBER 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_DISABLED 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L 6:6 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L 7:7 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L 9:8 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_DEFAULT 0x00000003 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_ACTIVE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_PARTIAL 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_SLUMBER 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_DISABLED 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L 10:10 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L 11:11 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L 13:12 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_DEFAULT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_PLL_05X 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_PLL_1X 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_PLL_2X 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L 15:14 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_DEFAULT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_PLL_05X 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_PLL_1X 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_PLL_2X 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_STAT_IDLE_1L 16:16 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_STAT_IDLE_1L_IDLE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_RX_STAT_IDLE_1L_SIG_PRESENT 0x00000000 /* R---V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_STAT_PRESENT_1L 17:17 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_STAT_PRESENT_1L_RX_PRSNT 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_STAT_PRESENT_1L_RX_ABSNT 0x00000000 /* R---V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS 19:19 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P 21:20 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_RD2REGOUT 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_WR2REGOUT 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_RD2RXOUT 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_WR2RXOUT 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS 22:22 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS 23:23 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P 26:24 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_CDR_CLK 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_CDR_DATA 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_IDLE_DET 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_RX_AMP 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS 27:27 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS 30:28 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_INVERITNG_17C 0x00000005 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_STATIC_01F 0x00000004 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_INVERITNG_333 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_STATIC_155 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_PRBS_27_1 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_NORMAL 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS 31:31 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_2 0x000000A4 /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_CTL_2_CDR_CNTL_1P 7:0 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_CDR_CNTL_1P_DEFAULT 0x00000010 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_MISC_CNTL_1P 11:8 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_MISC_CNTL_1P_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_RDET_T_1P 13:12 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_RDET_T_1P_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P 15:14 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_70_MVPPD 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_120_MVPPD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_100_MVPPD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_DIV_1L 17:16 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_DIV_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_DIV_1L_NORMAL 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_DIV_1L 19:18 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_DIV_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_DIV_1L_NORMAL 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_OUT_1L 20:20 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_OUT_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_IN_1L 21:21 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_DIR_1L 22:22 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_DIR_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_EN_1L 23:23 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_EN_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_OUT_1L 24:24 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_OUT_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_IN_1L 25:25 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_DIR_1L 26:26 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_DIR_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_EN_1L 27:27 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_EN_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_MODE_1L 28:28 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_MODE_1L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4 0x000000A8 /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS_BYPASS 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS_NORMAL 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS_BYPASS 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS_NORMAL 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P 6:4 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_DEFAULT 0x00000002 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_MIN 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_CENTERED 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_MAX 0x00000004 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS 7:7 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS 8:8 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS 12:12 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_ERROR_1L 13:13 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_ERROR_1L_ERROR 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_ERROR_1L_NO_ERROR 0x00000000 /* R---V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS 19:16 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_MODE_1P 23:20 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_MODE_1P_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_TERM_1P 24:24 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_TX_TERM_1P_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_RX_TERM_1P 25:25 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_RX_TERM_1P_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_SPARE_IN_GS 29:28 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_4_SPARE_IN_GS_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_4_SPARE_OUT_1L 31:30 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_CTL_5 0x000000AC /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C 5:0 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C_DEFAULT 0x00000020 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C_1150_MVPPD 0x00000026 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C_1000_MVPPD 0x00000020 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C__500_MVPPD 0x0000000C /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C__200_MVPPD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_CMADJ_R1_1C 11:8 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_CMADJ_R1_1C_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C 16:12 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_DEFAULT 0x0000000E /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_37DB 0x0000000E /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_60DB 0x00000014 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_PRE_R1_1C 19:17 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_PRE_R1_1C_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C 30:28 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C_NO_EQ 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C_MAX_EQ 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6 0x000000B0 /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C 5:0 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C_DEFAULT 0x00000020 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C_1150_MVPPD 0x00000026 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C_1000_MVPPD 0x00000020 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C__500_MVPPD 0x0000000C /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C__200_MVPPD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_CMADJ_R2_1C 11:8 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_CMADJ_R2_1C_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C 16:12 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_DEFAULT 0x0000000E /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_37DB 0x0000000E /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_60DB 0x00000014 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL1_1C 19:17 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL1_1C_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C 24:20 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_DEFAULT 0x00000014 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_37DB 0x0000000E /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_60DB 0x00000014 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL0_1C 27:25 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL0_1C_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C 30:28 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C_NO_EQ 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C_MAX_EQ 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_SEL 0x000000B4 /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT 31:0 /* RWIVF */ +#define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT_DEFAULT 0xFFFFFFFF /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT_NO_PLLS 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT_PLLS_31_0 0xFFFFFFFF /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1 0x000000B8 /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM 0:0 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM 1:1 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM_ASSERT 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM_DEASSERT 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST 2:2 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST_HOLD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST_RELEASE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R 4:4 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L 5:5 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M 6:6 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M_INDEPENDENT 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M_SHARED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD 7:7 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_LOCKDET 8:8 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_LOCKDET_NOT_LOCKED 0x00000000 /* R---V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_LOCKDET_LOCKED 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL 14:12 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV10 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV9 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV8 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV7 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV3 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN 15:15 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN_DEFAULT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL 17:16 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_INTERNAL_CML 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_INTERNAL_CMOS 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_EXTERNAL 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV 19:18 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_DEFAULT 0x00000002 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_10X 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_20X 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_25X 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_30X 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL 20:20 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL_DEFAULT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL_DIV10 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL_DIV5 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN 21:21 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN_DEFAULT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN 22:22 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN_DEFAULT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN 23:23 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN_DEFAULT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL 26:24 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_DIV10 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_DIV5 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_XDIGCLK 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_REFCLK 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_LFBCLK 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN 27:27 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100 28:28 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON 29:29 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN 31:31 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2 0x000000BC /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE 4:0 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_DEFAULT 0x0000000E /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_MAX_R 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_NOMINAL_R 0x0000000E /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_MIN_R 0x0000001F /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS 7:7 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS_DEFAULT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_VAL 12:8 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_VAL_MAX_R 0x00000000 /* R---V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_VAL_MIN_R 0x0000001F /* R---V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET 14:14 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_DONE 15:15 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_DONE_FALSE 0x00000000 /* R---V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_DONE_TRUE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL 17:16 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_NORMAL 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_POS_COEFF 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_NEG_COEFF 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_NORMAL_PLUS 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL 22:20 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_DEFAULT 0x00000004 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_15UA 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_17P5UA 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_20UA 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_22P5UA 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_25UA 0x00000005 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_27P5UA 0x00000006 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_30UA 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_MISC_CNTL 27:24 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_MISC_CNTL_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3 0x000000C0 /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ 0:0 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST 1:1 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST_ASSERT 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST_DEASSERT 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE 4:4 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE_PCIE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE_DISPLAY 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_LOCKDET 8:8 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_LOCKDET_NOT_LOCKED 0x00000000 /* R---V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_LOCKDET_LOCKED 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL 26:24 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_DIV5 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_DIV10 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_REFCLK 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_LFBCLK 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_TXCLKREF 0x00000006 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_TKOUT_IN 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN 27:27 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN 31:31 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4 0x000000C4 /* RW-4R */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ 0:0 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST 1:1 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST_ASSERT 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST_DEASSERT 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE 4:4 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE_PCIE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE_DISPLAY 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_LOCKDET 8:8 /* R--VF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_LOCKDET_NOT_LOCKED 0x00000000 /* R---V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_LOCKDET_LOCKED 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL 26:24 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_DIV5 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_DIV10 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_REFCLK 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_LFBCLK 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_TXCLKREF 0x00000006 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_TKOUT_IN 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN 27:27 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN 31:31 /* RWIUF */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN_ENABLED 0x00000001 /* RW--V */ + +#endif // ifndef ___DEV_AP_PCIE2_PADS_H_INC_ + diff --git a/arch/arm/mach-tegra/include/ap20/dev_ap_pcie2_root_port.h b/arch/arm/mach-tegra/include/ap20/dev_ap_pcie2_root_port.h new file mode 100644 index 000000000000..4f5e823383dd --- /dev/null +++ b/arch/arm/mach-tegra/include/ap20/dev_ap_pcie2_root_port.h @@ -0,0 +1,2085 @@ +/* + * Copyright (c) 2009 NVIDIA Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the NVIDIA Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef ___DEV_AP_PCIE2_ROOT_PORT_H_INC_ +#define ___DEV_AP_PCIE2_ROOT_PORT_H_INC_ + +#define NV_PROJ__PCIE2_RP 0x00000FFF:0x00000000 /* RW--D */ +#define NV_PROJ__PCIE2_RP_DEV_ID 0x00000000 /* R--4R */ +#define NV_PROJ__PCIE2_RP_DEV_ID_VENDOR_ID 15:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_ID_VENDOR_ID_NVIDIA 0x000010DE /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_ID_DEVICE_ID 31:16 /* R--VF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL 0x00000004 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_IO_SPACE 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_IO_SPACE_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_IO_SPACE_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_MEMORY_SPACE 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_BUS_MASTER 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_BUS_MASTER_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SPECIAL_CYCLE 3:3 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SPECIAL_CYCLE_DISABLED 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SPECIAL_CYCLE_ENABLED 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_WRITE_AND_INVAL 4:4 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_WRITE_AND_INVAL_DISABLED 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_WRITE_AND_INVAL_ENABLED 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_PALETTE_SNOOP 5:5 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_PALETTE_SNOOP_DISABLED 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_PALETTE_SNOOP_ENABLED 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_PERR 6:6 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_PERR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_PERR_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_STEP 7:7 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_STEP_DISABLED 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_STEP_ENABLED 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SERR 8:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SERR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SERR_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_BACK2BACK 9:9 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_BACK2BACK_DISABLED 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_BACK2BACK_ENABLED 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_DISABLE 10:10 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_DISABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_DISABLE_YES 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_DISABLE_NO 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_STATUS 19:19 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_STATUS_NOT_ACTIVE 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_STATUS_ACTIVE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_CAPLIST 20:20 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_CAPLIST_PRESENT 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_CAPLIST_NOT_PRESENT 0x00000000 /* ----V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_66MHZ 21:21 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_66MHZ_INCAPABLE 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_66MHZ_CAPABLE 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_FAST_BACK2BACK 23:23 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_FAST_BACK2BACK_INCAPABLE 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_FAST_BACK2BACK_CAPABLE 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_MASTER_DATA_PERR 24:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_MASTER_DATA_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_MASTER_DATA_PERR_ACTIVE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_MASTER_DATA_PERR_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_DEVSEL_TIMING 26:25 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_DEVSEL_TIMING_FAST 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_DEVSEL_TIMING_MEDIUM 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_DEVSEL_TIMING_SLOW 0x00000002 /* ----V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_TARGET 27:27 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_TARGET_NO_ABORT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_TARGET_ABORT 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_TARGET_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_TARGET 28:28 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_TARGET_NO_ABORT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_TARGET_ABORT 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_TARGET_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_MASTER 29:29 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_MASTER_NO_ABORT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_MASTER_ABORT 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_MASTER_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_SERR 30:30 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_SERR_NOT_ACTIVE 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_SERR_ACTIVE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_SERR_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_DETECTED_PERR 31:31 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_DETECTED_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_DETECTED_PERR_ACTIVE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_DEV_CTRL_DETECTED_PERR_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_REV_CC 0x00000008 /* R--4R */ +#define NV_PROJ__PCIE2_RP_REV_CC_REVISION_ID 7:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_REV_CC_CLASS_CODE 31:8 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_REV_CC_CLASS_CODE_P2P 0x00060400 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MISC_1 0x0000000C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_MISC_1_CACHE_LINE_SIZE 7:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_MISC_1_CACHE_LINE_SIZE_0_BYTES 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_MISC_1_PLATENCY_TIMER 15:11 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MISC_1_PLATENCY_TIMER_0_CLOCKS 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE0 22:16 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE0_NON_BRIDGE 0x00000000 /* ----V */ +#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE0_P2P_BRIDGE 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE1 23:23 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE1_SINGLEFUNC 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE1_MULTIFUNC 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_MISC_1_BIST 31:24 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MISC_1_BIST_ZERO 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_BAR_0 0x00000010 /* C--4R */ +#define NV_PROJ__PCIE2_RP_BAR_0_RESERVED 31:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_BAR_0_RESERVED_0 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_BAR_1 0x00000014 /* C--4R */ +#define NV_PROJ__PCIE2_RP_BAR_1_RESERVED 31:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_BAR_1_RESERVED_0 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_BN_LT 0x00000018 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_BN_LT_PRI_BUS_NUMBER 7:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_BN_LT_PRI_BUS_NUMBER_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_BN_LT_SEC_BUS_NUMBER 15:8 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_BN_LT_SEC_BUS_NUMBER_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_BN_LT_SEC_BUS_NUMBER_1 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_BN_LT_SEC_BUS_NUMBER_2 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_BN_LT_SEC_BUS_NUMBER_255 0x000000ff /* RW--V */ +#define NV_PROJ__PCIE2_RP_BN_LT_SUB_BUS_NUMBER 23:16 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_BN_LT_SUB_BUS_NUMBER_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_BN_LT_SUB_BUS_NUMBER_1 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_BN_LT_SUB_BUS_NUMBER_2 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_BN_LT_SUB_BUS_NUMBER_255 0x000000ff /* RW--V */ +#define NV_PROJ__PCIE2_RP_BN_LT_SLATENCY_TIMER 31:27 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_BN_LT_SLATENCY_TIMER_0_CLOCKS 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS 0x0000001C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_SUPPORT 3:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_SUPPORT_16 0x00000000 /* ----V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_SUPPORT_32 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE 7:4 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_ADDRESS_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_ADDRESS_256 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_ADDRESS_512 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_ADDRESS_64K 0x0000000f /* RW--V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_SUPPORT 11:8 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_SUPPORT_16 0x00000000 /* ----V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_SUPPORT_32 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT 15:12 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_ADDRESS_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_ADDRESS_256 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_ADDRESS_512 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_ADDRESS_64K 0x0000000f /* RW--V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_66MHZ 21:21 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_66MHZ_INCAPABLE 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_66MHZ_CAPABLE 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_FAST_BACK2BACK 23:23 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_FAST_BACK2BACK_INCAPABLE 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_FAST_BACK2BACK_CAPABLE 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_MASTER_DATA_PERR 24:24 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_MASTER_DATA_PERR_NOT_ACTIVE 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_MASTER_DATA_PERR_ACTIVE 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_DEVSEL_TIMING 26:25 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_DEVSEL_TIMING_FAST 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_DEVSEL_TIMING_MEDIUM 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_DEVSEL_TIMING_SLOW 0x00000002 /* ----V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_SIGNALED_TARGET 27:27 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_SIGNALED_TARGET_NO_ABORT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_SIGNALED_TARGET_ABORT 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_SIGNALED_TARGET_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_TARGET 28:28 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_TARGET_NO_ABORT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_TARGET_ABORT 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_TARGET_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_MASTER 29:29 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_MASTER_NO_ABORT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_MASTER_ABORT 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_MASTER_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_SERR 30:30 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_SERR_NOT_ACTIVE 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_SERR_ACTIVE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_SERR_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_DETECTED_PERR 31:31 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_DETECTED_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_DETECTED_PERR_ACTIVE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_IO_BL_SS_DETECTED_PERR_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_MEM_BL 0x00000020 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_BASE 15:4 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_BASE_ADDRESS_0 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_BASE_ADDRESS_1MEG 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_BASE_ADDRESS_2MEG 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_BASE_ADDRESS_4GIG 0x00000fff /* RW--V */ +#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_LIMIT 31:20 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_LIMIT_ADDRESS_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_LIMIT_ADDRESS_1MEG 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_LIMIT_ADDRESS_2MEG 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_LIMIT_ADDRESS_4GIG 0x00000fff /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRE_BL 0x00000024 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRE_BL_B64BIT 3:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PRE_BL_B64BIT_YES 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_BASE 15:4 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_BASE_ADDRESS_0 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_BASE_ADDRESS_1MEG 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_BASE_ADDRESS_2MEG 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_BASE_ADDRESS_4GIG 0x00000fff /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRE_BL_L64BIT 19:16 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PRE_BL_L64BIT_YES 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_LIMIT 31:20 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_LIMIT_ADDRESS_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_LIMIT_ADDRESS_1MEG 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_LIMIT_ADDRESS_2MEG 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_LIMIT_ADDRESS_4GIG 0x00000fff /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRE_BU32 0x00000028 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRE_BU32_BASE_UPPER_BITS 31:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_PRE_BU32_BASE_UPPER_BITS_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRE_LU32 0x0000002C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRE_LU32_LIMIT_UPPER_BITS 31:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_PRE_LU32_LIMIT_UPPER_BITS_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_U16 0x00000030 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_IO_BL_U16_BASE_UPPER_BITS 15:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_IO_BL_U16_BASE_UPPER_BITS_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_IO_BL_U16_LIMIT_UPPER_BITS 31:16 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_IO_BL_U16_LIMIT_UPPER_BITS_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CAP_PTR 0x00000034 /* C--4R */ +#define NV_PROJ__PCIE2_RP_CAP_PTR_CAP_PTR 7:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_CAP_PTR_CAP_PTR_PM 0x00000040 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_ROM_BA 0x00000038 /* C--4R */ +#define NV_PROJ__PCIE2_RP_ROM_BA_RESERVED 31:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_ROM_BA_RESERVED_0 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR 0x0000003C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_LINE 7:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_LINE_IRQ0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_LINE_IRQ1 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_LINE_IRQ15 0x0000000F /* RW--V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_LINE_UNKNOWN 0x000000FF /* RW--V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN 15:8 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN_NONE 0x00000000 /* ----V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN_INTA 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN_INTB 0x00000002 /* ----V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN_INTC 0x00000003 /* ----V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN_INTD 0x00000004 /* ----V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_PERR_RESP 16:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_PERR_RESP_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_PERR_RESP_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_SERR_FORWARD 17:17 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_SERR_FORWARD_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_SERR_FORWARD_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_ISA_ADDRESS 18:18 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_ISA_ADDRESS_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_ISA_ADDRESS_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_ADDRESS 19:19 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_ADDRESS_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_ADDRESS_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_16BITIO 20:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_16BITIO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_16BITIO_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_MABORT 21:21 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_MABORT_DISABLED 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_MABORT_ENABLED 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_SB_RESET 22:22 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_SB_RESET_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_SB_RESET_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_FAST_B2B 23:23 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_FAST_B2B_DISABLED 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_FAST_B2B_ENABLED 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_PRIMARY_DIS_TIMER 24:24 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_PRIMARY_DIS_TIMER_LONG 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_PRIMARY_DIS_TIMER_SHORT 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_SECONDARY_DIS_TIMER 25:25 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_SECONDARY_DIS_TIMER_LONG 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_SECONDARY_DIS_TIMER_SHORT 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_STATUS 26:26 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_STATUS_NOT_ACTIVE 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_STATUS_ACTIVE 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_SERR 27:27 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_SERR_DISABLED 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_SERR_ENABLED 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_SS_0 0x00000040 /* R--4R */ +#define NV_PROJ__PCIE2_RP_SS_0_NEXT_PTR 15:8 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_SS_0_NEXT_PTR_PM 0x48 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_SS_0_CAP_ID 7:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_SS_0_CAP_ID_SS 0x0D /* C-I-V */ +#define NV_PROJ__PCIE2_RP_SS_1 0x00000044 /* R--4R */ +#define NV_PROJ__PCIE2_RP_SS_1_SSID 31:16 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_SS_1_SSID_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SS_1_SSVID 15:0 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_SS_1_SSVID_INIT 0x10DE /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PM_0 0x00000048 /* R--4R */ +#define NV_PROJ__PCIE2_RP_PM_0_PME_SUPPORT 31:27 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_0_PME_SUPPORT_YES 0x0000001F /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_0_PME_SUPPORT_NO 0x00000000 /* ----V */ +#define NV_PROJ__PCIE2_RP_PM_0_D2_SUPPORT 26:26 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_0_D2_SUPPORT_YES 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_PM_0_D2_SUPPORT_NO 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_0_D1_SUPPORT 25:25 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_0_D1_SUPPORT_YES 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_PM_0_D1_SUPPORT_NO 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_0_AUX_CURRENT 24:22 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_0_AUX_CURRENT_0 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_0_DEV_SPEC_INIT 21:21 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_0_DEV_SPEC_INIT_NOT_NEEDED 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_0_DEV_SPEC_INIT_NEEDED 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_PM_0_PME_CLOCK 19:19 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_0_PME_CLOCK_NOT_NEEDED 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_0_PME_CLOCK_NEEDED 0x00000001 /* ----V */ +#define NV_PROJ__PCIE2_RP_PM_0_PCIPM_REV 18:16 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_0_PCIPM_REV_12 0x00000003 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_0_PCIPM_REV_11 0x00000002 /* ----V */ +#define NV_PROJ__PCIE2_RP_PM_0_NEXT_PTR 15:8 /* R--VF */ +#define NV_PROJ__PCIE2_RP_PM_0_CAP_ID 7:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_0_CAP_ID_PM 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_1 0x0000004C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA 31:24 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA_UNS 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_BPCC 23:23 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_BPCC_UNS 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_B2B3 22:22 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_B2B3_UNS 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_STATUS 15:15 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_STATUS_NOT_ACTIVE 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_STATUS_ACTIVE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_STATUS_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA_SCALE 14:13 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA_SCALE_UNS 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA_SEL 12:9 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA_SEL_UNS 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PM_1_PME 8:8 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_DISABLE 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PM_1_PME_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PM_1_PWR_STATE 1:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PM_1_PWR_STATE_D0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PM_1_PWR_STATE_D1 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PM_1_PWR_STATE_D2 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PM_1_PWR_STATE_D3HOT 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL 0x00000050 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_RSVD 31:24 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_RSVD_0 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_64BIT_CAP 23:23 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_64BIT_CAP_TRUE 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_EN 22:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_EN_CODE0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_EN_CODE2 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_EN_CODE4 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_EN_CODE8 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_CAP 19:17 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_CAP_CODE2 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_MSI 16:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_MSI_DISABLE 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_MSI_ENABLE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_NEXT_PTR 15:8 /* R--VF */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_NEXT_PTR_MSIMAP 0x00000060 /* R---V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_NEXT_PTR_PCIEXP 0x00000080 /* R---V */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_CAP_ID 7:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MSI_CTRL_CAP_ID_MSI 0x00000005 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MSI_LOW_ADDR 0x00000054 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_MSI_LOW_ADDR_DWORD 31:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_MSI_LOW_ADDR_DWORD_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MSI_LOW_ADDR_RSVD 1:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MSI_LOW_ADDR_RSVD_0 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MSI_UPPER_ADDR 0x00000058 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_MSI_UPPER_ADDR_DWORD 31:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_MSI_UPPER_ADDR_DWORD_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MSI_DATA 0x0000005C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_MSI_DATA_RSVD 31:16 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MSI_DATA_RSVD_0 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MSI_DATA_NON_RSVD 15:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_MSI_DATA_NON_RSVD_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MSIMAP_0 0x00000060 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_ID 7:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_ID_LDT 0x00000008 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_PTR 15:8 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_PTR_PCIEXP 0x00000080 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MSIMAP_0_XLATE_ENABLE 16:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_MSIMAP_0_XLATE_ENABLE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_TYPE 31:27 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_TYPE_MSI 0x00000015 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_MSIMAP_1 0x00000064 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_MSIMAP_1_ADDRESS_LOWER 31:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_MSIMAP_1_ADDRESS_LOWER_DEFAULT 0x00000FEE /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MSIMAP_2 0x00000068 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_MSIMAP_2_ADDRESS_UPPER 31:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_MSIMAP_2_ADDRESS_UPPER_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY 0x00000080 /* R--4R */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID 7:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID_INIT 0x00000010 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR 15:8 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_VERSION 19:16 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_VERSION_INIT 0x00000002 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_VERSION_1 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_VERSION_2 0x00000002 /* R---V */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE 23:20 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE_INIT 0x00000004 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED 24:24 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED_INIT 0x00000001 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER 29:25 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER_ZERO 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY 0x00000084 /* R--4R */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE 2:0 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_INIT 0x00000001 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED 4:3 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE 5:5 /* R--VF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ENDPOINT_L0S_ACCEPTABLE_LATENCY 8:6 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ENDPOINT_L0S_ACCEPTABLE_LATENCY_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ENDPOINT_L1_ACCEPTABLE_LATENCY 11:9 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ENDPOINT_L1_ACCEPTABLE_LATENCY_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ATTENTION_BUTTON_PRESENT 12:12 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ATTENTION_BUTTON_PRESENT_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ATTENTION_INDICATOR_PRESENT 13:13 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ATTENTION_INDICATOR_PRESENT_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_POWER_INDICATOR_PRESENT 14:14 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_POWER_INDICATOR_PRESENT_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING 15:15 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING_INIT 0x1 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE 25:18 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE 27:26 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS 0x00000088 /* RWI4R */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE 3:3 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE 7:5 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE 9:9 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE 10:10 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE 14:12 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE_INIT 0x00000002 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED 16:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED 19:19 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED 20:20 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LINK_CAPABILITIES 0x0000008C /* R--4R */ +#define NV_PROJ__PCIE2_RP_LINK_CAPABILITIES_LINKCAP 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS 0x00000090 /* RWI4R */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL 1:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY 3:3 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_LINK_DISABLE 4:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_LINK_DISABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_RETRAIN_LINK 5:5 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_RETRAIN_LINK_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION 6:6 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_EXTENDED_SYNCH 7:7 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_EXTENDED_SYNCH_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_CLOCK_PM 8:8 /* C--VF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_CLOCK_PM_DEFAULT 0x00000000 /* C---V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_HW_AUTO_WIDTH_DISABLE 9:9 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_HW_AUTO_WIDTH_DISABLE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT_INT_EN 10:10 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT_INT_EN_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH_INT_EN 11:11 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH_INT_EN_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_LINKSTAT 29:16 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT 30:30 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT_TRUE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT_FALSE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT_SET 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH 31:31 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH_TRUE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH_FALSE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH_SET 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES 0x00000094 /* R--4R */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_ATTENTION_BUTTON_PRESENT 0:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_POWER_CONTROLLER_PRESENT 1:1 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_MRL_SENSOR_PRESENT 2:2 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_ATTENTION_INDICATOR_PRESENT 3:3 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_POWER_INDICATOR_PRESENT 4:4 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_HOT_PLUG_SURPRISE 5:5 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_HOT_PLUG_CAPABLE 6:6 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_VALUE 14:7 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_SCALE 16:15 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_ELECTROMECHANICAL_INTERLOCK_PRESENT 17:17 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_NO_CMD_COMPLETED_SUPPORT 18:18 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_PHYSICAL_SLOT_NUMBER 31:19 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS 0x00000098 /* RWI4R */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE 3:3 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE 4:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE 5:5 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL 7:6 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL_INIT 0x00000003 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL 9:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL 10:10 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL 11:11 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL_INIT 0x000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_DL_LAYER_STATE_CHANGED_ENABLE 12:12 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_DL_LAYER_STATE_CHANGED_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED 16:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED 17:17 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED 18:18 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED 19:19 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_COMMAND_COMPLETED 20:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE 21:21 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE 22:22 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE_YES 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATE 23:23 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATE_YES 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_DL_LAYER_STATE_CHANGED 24:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_DL_LAYER_STATE_CHANGED_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_DL_LAYER_STATE_CHANGED_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RCR 0x0000009C /* RWI4R */ +#define NV_PROJ__PCIE2_RP_RCR_SERR_COR 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_RCR_SERR_COR_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RCR_SERR_NONFAT 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_RCR_SERR_NONFAT_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RCR_SERR_FAT 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_RCR_SERR_FAT_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RCR_PME_INT 3:3 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_RCR_PME_INT_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RSR 0x000000A0 /* RWI4R */ +#define NV_PROJ__PCIE2_RP_RSR_REQID 15:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_RSR_PMESTAT 16:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_RSR_PMESTAT_NOT_ACTIVE 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RSR_PMESTAT_ACTIVE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_RSR_PMESTAT_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RSR_PMEPEND 17:17 /* R--VF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2 0x000000A4 /* C-I4R */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_CPL_TO_RANGES_SUP 3:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_CPL_TO_RANGES_SUP_0 0x00000003 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_CPL_TO_DIS_SUP 4:4 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_CPL_TO_DIS_SUP_0 0x00000001 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_RESERVED 31:5 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_RESERVED_0 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2 0x000000A8 /* RWI4R */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE 3:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE_RANGE_A_LO 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE_RANGE_A_HI 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE_RANGE_B_LO 0x00000005 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE_RANGE_B_HI 0x00000006 /* RW--V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_DISABLE 4:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_DISABLE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_RESERVED 31:5 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_RESERVED_0 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CAPABILITIES_2 0x000000AC /* C--4R */ +#define NV_PROJ__PCIE2_RP_LINK_CAPABILITIES_2_BITS 31:0 /* C--VF */ +#define NV_PROJ__PCIE2_RP_LINK_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2 0x000000B0 /* RWI4R */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED 3:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_GEN2_DIS 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_2P5 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_5P0 0x00000002 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE 4:4 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE 5:5 /* C--VF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE_INIT 0x00000000 /* C---V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_SELECTABLE_DEEMPHASIS 6:6 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN 9:7 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_ENTER_MODIFIED_COMPLIANCE 10:10 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_ENTER_MODIFIED_COMPLIANCE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS 11:11 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_COMPLIANCE_DEEMPHASIS 12:12 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_COMPLIANCE_DEEMPHASIS_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_RESERVED_CONTROL 15:13 /* C--VF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_RESERVED_CONTROL_DEFAULT 0x00000000 /* C---V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_CURRENT_DEEMPHASIS_LEVEL 16:16 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_CURRENT_DEEMPHASIS_LEVEL_3P5 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_CURRENT_DEEMPHASIS_LEVEL_6 0x00000000 /* R---V */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_RESERVED_STATUS 31:17 /* C--VF */ +#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_RESERVED_STATUS_DEFAULT 0x00000000 /* C---V */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_2 0x000000B4 /* C--4R */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_2_BITS 31:0 /* C--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_2 0x000000B8 /* C--4R */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_2_BITS 31:0 /* C--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP 0x00000100 /* R--4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ID 15:0 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ID_AER 0x0001 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_VERSION 19:16 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_VERSION_1 0x1 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_NEXT_PTR 31:20 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_NEXT_PTR_NONE 0x000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR 0x00000104 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_TRAINING_ERR 0:0 /* C--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_TRAINING_ERR_DEFAULT 0x0 /* C---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_DLINK_PROTO_ERR 4:4 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_DLINK_PROTO_ERR_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_DLINK_PROTO_ERR_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_DLINK_PROTO_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_POS_TLP 12:12 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_POS_TLP_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_POS_TLP_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_POS_TLP_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_FC_PROTO_ERR 13:13 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_FC_PROTO_ERR_DEFAULT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_FC_PROTO_ERR_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_FC_PROTO_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_TO 14:14 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_TO_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_TO_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_TO_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_ABORT 15:15 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_ABORT_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_ABORT_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_ABORT_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNEXP_COMP 16:16 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNEXP_COMP_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNEXP_COMP_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNEXP_COMP_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_RCV_OVFL 17:17 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_RCV_OVFL_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_RCV_OVFL_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_RCV_OVFL_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MF_TLP 18:18 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MF_TLP_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MF_TLP_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MF_TLP_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_ECRC_ERR 19:19 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_ECRC_ERR_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_ECRC_ERR_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_ECRC_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNSUP_REQ_ERR 20:20 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNSUP_REQ_ERR_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNSUP_REQ_ERR_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNSUP_REQ_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK 0x00000108 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_TRAINING_ERR 0:0 /* C--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_TRAINING_ERR_DEFAULT 0x0 /* C---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_DLINK_PROTO_ERR 4:4 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_DLINK_PROTO_ERR_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_DLINK_PROTO_ERR_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_POS_TLP 12:12 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_POS_TLP_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_POS_TLP_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_FC_PROTO_ERR 13:13 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_FC_PROTO_ERR_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_FC_PROTO_ERR_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_TO 14:14 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_TO_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_TO_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_ABORT 15:15 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_ABORT_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_ABORT_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNEXP_COMP 16:16 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNEXP_COMP_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNEXP_COMP_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_RCV_OVFL 17:17 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_RCV_OVFL_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_RCV_OVFL_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_MF_TLP 18:18 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_MF_TLP_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_MF_TLP_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_ECRC_ERR 19:19 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_ECRC_ERR_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_ECRC_ERR_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNSUP_REQ_ERR 20:20 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNSUP_REQ_ERR_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNSUP_REQ_ERR_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR 0x0000010C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_TRAINING_ERR 0:0 /* C--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_TRAINING_ERR_NON_FATAL 0x0 /* ----V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_TRAINING_ERR_FATAL 0x1 /* C---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_DLINK_PROTO_ERR 4:4 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_DLINK_PROTO_ERR_NON_FATAL 0x0 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_DLINK_PROTO_ERR_FATAL 0x1 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_POS_TLP 12:12 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_POS_TLP_NON_FATAL 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_POS_TLP_FATAL 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_FC_PROTO_ERR 13:13 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_FC_PROTO_ERR_NON_FATAL 0x0 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_FC_PROTO_ERR_FATAL 0x1 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_TO 14:14 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_TO_NON_FATAL 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_TO_FATAL 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_ABORT 15:15 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_ABORT_NON_FATAL 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_ABORT_FATAL 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNEXP_COMP 16:16 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNEXP_COMP_NON_FATAL 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNEXP_COMP_FATAL 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_RCV_OVFL 17:17 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_RCV_OVFL_NON_FATAL 0x0 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_RCV_OVFL_FATAL 0x1 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_MF_TLP 18:18 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_MF_TLP_NON_FATAL 0x0 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_MF_TLP_FATAL 0x1 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_ECRC_ERR 19:19 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_ECRC_ERR_NON_FATAL 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_ECRC_ERR_FATAL 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNSUP_REQ_ERR 20:20 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNSUP_REQ_ERR_NON_FATAL 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNSUP_REQ_ERR_FATAL 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR 0x00000110 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RCV_ERR 0:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RCV_ERR_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RCV_ERR_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RCV_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_TLP 6:6 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_TLP_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_TLP_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_TLP_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_DLLP 7:7 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_DLLP_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_DLLP_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_DLLP_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_RLOV 8:8 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_RLOV_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_RLOV_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_RLOV_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_TO 12:12 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_TO_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_TO_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_TO_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_ADVISORY_NF 13:13 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_ADVISORY_NF_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_ADVISORY_NF_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_ADVISORY_NF_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK 0x00000114 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RCV_ERR 0:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RCV_ERR_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RCV_ERR_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_TLP 6:6 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_TLP_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_TLP_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_DLLP 7:7 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_DLLP_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_DLLP_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_RLOV 8:8 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_RLOV_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_RLOV_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_TO 12:12 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_TO_NOT_MASKED 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_TO_MASKED 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_ADVISORY_NF 13:13 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_ADVISORY_NF_NOT_MASKED 0x0 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_ADVISORY_NF_MASKED 0x1 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL 0x00000118 /* R--4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ERR_PTR 4:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_GEN_CAP 5:5 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_GEN_CAP_TRUE 0x1 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_GEN_EN 6:6 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_GEN_EN_FALSE 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_GEN_EN_TRUE 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_CHK_CAP 7:7 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_CHK_CAP_TRUE 0x1 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_CHK_EN 8:8 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_CHK_EN_FALSE 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_CHK_EN_TRUE 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW0 0x0000011C /* R--4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW0_0 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW1 0x00000120 /* R--4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW1_1 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW2 0x00000124 /* R--4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW2_2 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW3 0x00000128 /* R--4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW3_3 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD 0x0000012C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_COR_ERR_RPT_EN 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_COR_ERR_RPT_EN_FALSE 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_COR_ERR_RPT_EN_TRUE 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_NONFATAL_ERR_RPT_EN 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_NONFATAL_ERR_RPT_EN_FALSE 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_NONFATAL_ERR_RPT_EN_TRUE 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_FATAL_ERR_RPT_EN 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_FATAL_ERR_RPT_EN_FALSE 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_FATAL_ERR_RPT_EN_TRUE 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS 0x00000130 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_COR_RCVD 0:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_COR_RCVD_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_COR_RCVD_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_COR_RCVD_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_COR_RCVD 1:1 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_COR_RCVD_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_COR_RCVD_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_COR_RCVD_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_UNCOR_RCVD 2:2 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_UNCOR_RCVD_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_UNCOR_RCVD_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_UNCOR_RCVD_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_UNCOR_RCVD 3:3 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_UNCOR_RCVD_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_UNCOR_RCVD_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_UNCOR_RCVD_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FIRST_FATAL_RCVD 4:4 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FIRST_FATAL_RCVD_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FIRST_FATAL_RCVD_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FIRST_FATAL_RCVD_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_NONFATAL_RCVD 5:5 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_NONFATAL_RCVD_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_NONFATAL_RCVD_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_NONFATAL_RCVD_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FATAL_RCVD 6:6 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FATAL_RCVD_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FATAL_RCVD_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FATAL_RCVD_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_ADV_ERR_INTR_MSG_NUM 31:27 /* R--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_ID 0x00000134 /* R--4R */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_ID_ERR_COR 15:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_ID_ERR_COR_DEFAULT 0x0000 /* R---V */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_ID_ERR_UNCOR 31:16 /* R--VF */ +#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_ID_ERR_UNCOR_DEFAULT 0x0000 /* R---V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0 0x00000494 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_DL_TIMERS_DISABLE 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_DL_TIMERS_DISABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_UPDATE_FC_THRESHOLD 9:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_UPDATE_FC_THRESHOLD_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_ACK_TIMER_LIMIT 18:10 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_ACK_TIMER_LIMIT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_REPLAY_TIMER_LIMIT 29:19 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_REPLAY_TIMER_LIMIT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_DBG0 0x00000D00 /* RWC4R */ +#define NV_PROJ__PCIE2_RP_DBG0_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_DBG0_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DBG1 0x00000D04 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_DBG1_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_DBG1_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DBG2 0x00000D08 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_DBG2_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_DBG2_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DBG3 0x00000D0C /* RWC4R */ +#define NV_PROJ__PCIE2_RP_DBG3_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_DBG3_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DBG4 0x00000D10 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_DBG4_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_DBG4_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DBG5 0x00000D14 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_DBG5_CTL 29:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_DBG5_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DBG5_CG_EN 30:30 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_DBG5_CG_EN_INIT 0x0 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DBG5_LOW_POWER_MODE 31:31 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_DBG5_LOW_POWER_MODE_INIT 0x1 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_DBG_RD_BACK_LO 0x00000D18 /* R--4R */ +#define NV_PROJ__PCIE2_RP_DBG_RD_BACK_LO_VALUE 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_DBG_RD_BACK_HI 0x00000D1C /* R--4R */ +#define NV_PROJ__PCIE2_RP_DBG_RD_BACK_HI_VALUE 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LANE_DBG0 0x00000D20 /* RWC4R */ +#define NV_PROJ__PCIE2_RP_LANE_DBG0_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LANE_DBG0_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LANE_DBG1 0x00000D24 /* RWC4R */ +#define NV_PROJ__PCIE2_RP_LANE_DBG1_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LANE_DBG1_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LANE_DBG2 0x00000D28 /* RWC4R */ +#define NV_PROJ__PCIE2_RP_LANE_DBG2_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LANE_DBG2_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LANE_DBG3 0x00000D2C /* RWC4R */ +#define NV_PROJ__PCIE2_RP_LANE_DBG3_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LANE_DBG3_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LANE_DBG4 0x00000D30 /* RWC4R */ +#define NV_PROJ__PCIE2_RP_LANE_DBG4_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LANE_DBG4_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LANE_DBG5 0x00000D34 /* RWC4R */ +#define NV_PROJ__PCIE2_RP_LANE_DBG5_CTL 29:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LANE_DBG5_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LANE_DBG5_CG_EN 30:30 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LANE_DBG5_CG_EN_INIT 0x0 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LANE_DBG5_LOW_POWER_MODE 31:31 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LANE_DBG5_LOW_POWER_MODE_INIT 0x1 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LANE_DBG_RD_BACK_LO 0x00000D38 /* R--4R */ +#define NV_PROJ__PCIE2_RP_LANE_DBG_RD_BACK_LO_VALUE 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LANE_DBG_RD_BACK_HI 0x00000D3C /* R--4R */ +#define NV_PROJ__PCIE2_RP_LANE_DBG_RD_BACK_HI_VALUE 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LINK_DBG0 0x00000D40 /* RWC4R */ +#define NV_PROJ__PCIE2_RP_LINK_DBG0_CTL 31:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_DBG0_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LINK_DBG1 0x00000D44 /* RWC4R */ +#define NV_PROJ__PCIE2_RP_LINK_DBG1_CTL 29:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_DBG1_CTL_INIT 0x00000000 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LINK_DBG1_CG_EN 30:30 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_DBG1_CG_EN_INIT 0x0 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LINK_DBG1_LOW_POWER_MODE 31:31 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LINK_DBG1_LOW_POWER_MODE_INIT 0x1 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_LINK_DBG_RD_BACK_LO 0x00000D48 /* R--4R */ +#define NV_PROJ__PCIE2_RP_LINK_DBG_RD_BACK_LO_VALUE 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LINK_DBG_RD_BACK_HI 0x00000D4C /* R--4R */ +#define NV_PROJ__PCIE2_RP_LINK_DBG_RD_BACK_HI_VALUE 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_RXL_DBG_RD_BACK 0x00000D50 /* R--4R */ +#define NV_PROJ__PCIE2_RP_RXL_DBG_RD_BACK_VALUE 31:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA 0x00000D54 /* RWC4R */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFI2UBFI 0:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFI2UBFI_INIT 0x00000001 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFIRSP 1:1 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFIRSP_INIT 0x00000001 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFIREQ 2:2 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFIREQ_INIT 0x00000001 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_PCA 3:3 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_PCA_INIT 0x00000001 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_UBFI2DFI_NTT 4:4 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_UBFI2DFI_NTT_INIT 0x00000001 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_CMDQ2UFARB 5:5 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_CMDQ2UFARB_INIT 0x00000001 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_TXBA2DFI_WR 6:6 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_TXBA2DFI_WR_INIT 0x00000001 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_UBFI2DFI_P2P 7:7 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_UBFI2DFI_P2P_INIT 0x00000001 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_UFA2WRR_PWTOP 8:8 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PIPE_CYA_UFA2WRR_PWTOP_INIT 0x00000001 /* RWC-V */ +#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT 0x00000E00 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_NP 7:0 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_NP_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_PW 15:8 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_PW_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_CPL 23:16 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_CPL_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT 0x00000E04 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_NP 7:0 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_NP_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_PW 19:8 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_PW_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_CPL 27:20 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_CPL_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT 0x00000E08 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_NP 7:0 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_NP_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_PW 15:8 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_PW_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_CPL 23:16 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_CPL_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_NPT 31:24 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_NPT_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_DATA_LIMIT 0x00000E0C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_TX_DATA_LIMIT_NP 7:0 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_TX_DATA_LIMIT_NP_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_DATA_LIMIT_PW 15:8 /* RWCUF */ +#define NV_PROJ__PCIE2_RP_TX_DATA_LIMIT_PW_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_UFPCI 0x00000E10 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_UFPCI_PW_STARV_COUNT 4:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_UFPCI_PW_STARV_COUNT_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_UFPCI_PW_PRI_OVR_COUNT 9:5 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_UFPCI_PW_PRI_OVR_COUNT_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_UFPCI_WRR_GRANT_BURST 11:10 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_UFPCI_WRR_GRANT_BURST_INIT 0x1 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_UFPCI_REQ_PEND_PERIOD 19:12 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_UFPCI_REQ_PEND_PERIOD_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_UFPCI_ISONP2HPISO 20:20 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_UFPCI_ISONP2HPISO_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_UFPCI_ISOPW2HPISO 21:21 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_UFPCI_ISOPW2HPISO_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0 0x00000E14 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_MISC0_ENABLE_CLUMPING 0:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_ENABLE_CLUMPING_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_NATIVE_P2P_ENABLE 1:1 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_NATIVE_P2P_ENABLE_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_ISO_NP_ENABLE 2:2 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_ISO_NP_ENABLE_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_ISO_PW_ENABLE 3:3 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_ISO_PW_ENABLE_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_BURST_SIZE 19:4 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_BURST_SIZE_INIT 0xFF /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_RXL_CLEAR_DROP 20:20 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_RXL_CLEAR_DROP_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_AUTO_XCLK_FREQ_EN 21:21 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_AUTO_XCLK_FREQ_EN_INIT 0x1 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_NISONC2HPISO 23:23 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_NISONC2HPISO_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_A 24:24 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_A_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_A__PROD 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_B 25:25 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_B_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_B__PROD 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_C 26:26 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_C_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_C__PROD 0x0 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_D 27:27 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_D_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_D__PROD 0x0 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_E 28:28 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_E_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_E__PROD 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_F 29:29 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_F_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_F__PROD 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_SMALL_ISA_HOLE 30:30 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_SMALL_ISA_HOLE_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_MISC0_P2P_SMALL_ISA_HOLE__PROD 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_MISC0_SHORT_RXL_TIMER 31:31 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_MISC0_SHORT_RXL_TIMER_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TXBA0 0x00000E18 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_TXBA0_REPLAY_BUF_LIMIT 8:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TXBA0_REPLAY_BUF_LIMIT_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_DISABLE 9:9 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_DISABLE_INIT 0x1 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_UPTO_32DW 10:10 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_UPTO_32DW_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_UPTO_64DW 11:11 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_UPTO_64DW_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TXBA0_USE_REPLAY_TIMER_OFFSET 12:12 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TXBA0_USE_REPLAY_TIMER_OFFSET_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TXBA0_USE_REPLAY_TIMER_OFFSET__PROD 0x1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_TXBA0_REPLAY_TIMER_EXPIRY 31:16 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TXBA0_REPLAY_TIMER_EXPIRY_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TXBA0_REPLAY_TIMER_EXPIRY__PROD 0x64 /* RW--V */ +#define NV_PROJ__PCIE2_RP_TXBA1 0x00000E1C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_TXBA1_PW_OVER_CM_BURST 3:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TXBA1_PW_OVER_CM_BURST_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TXBA1_CM_OVER_PW_BURST 7:4 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TXBA1_CM_OVER_PW_BURST_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TXBA1_CMPL_MERGE_THRESHOLD 15:8 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TXBA1_CMPL_MERGE_THRESHOLD_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_FORCEFC 0x00000E20 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_FORCEFC_PWH_UNRET_THRESH 7:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_FORCEFC_PWH_UNRET_THRESH_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_FORCEFC_PWD_UNRET_THRESH 15:8 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_FORCEFC_PWD_UNRET_THRESH_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_FORCEFC_NPH_UNRET_THRESH 23:16 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_FORCEFC_NPH_UNRET_THRESH_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_FORCEFC_NPD_UNRET_THRESH 31:24 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_FORCEFC_NPD_UNRET_THRESH_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TIMEOUT0 0x00000E24 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_PWRUP 7:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_PWRUP_INIT 0xD /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_PWRUP_CM 23:8 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_PWRUP_CM_INIT 0x14 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_SPDCHNG_GEN2 31:24 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_SPDCHNG_GEN2_INIT 0xD /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TIMEOUT1 0x00000E28 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_TIMEOUT1_PAD_SPDCHNG_GEN1 15:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TIMEOUT1_PAD_SPDCHNG_GEN1_INIT 0x2E8 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TIMEOUT1_RCVRY_SPD_SUCCESS_EIDLE 23:16 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TIMEOUT1_RCVRY_SPD_SUCCESS_EIDLE_INIT 0x14 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TIMEOUT1_RCVRY_SPD_UNSUCCESS_EIDLE 31:24 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_TIMEOUT1_RCVRY_SPD_UNSUCCESS_EIDLE_INIT 0x96 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR 0x00000E2C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_DBUF 0:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_DBUF_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_DBUF_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_DBUF_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_HBUF 1:1 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_HBUF_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_HBUF_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_HBUF_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY 2:2 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID0 3:3 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID0_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID0_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID0_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID1 4:4 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID1_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID1_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID1_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF 5:5 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF 6:6 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_NP_SIDEQ 7:7 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_NP_SIDEQ_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_NP_SIDEQ_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_NP_SIDEQ_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_PW_SIDEQ 8:8 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_PW_SIDEQ_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_PW_SIDEQ_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_PW_SIDEQ_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_UCFIFO 9:9 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_UCFIFO_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_UCFIFO_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_UCFIFO_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO1 10:10 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO1_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO1_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO1_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO2 11:11 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO2_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO2_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO2_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_DBUF 12:12 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_DBUF_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_DBUF_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_DBUF_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_HBUF 13:13 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_HBUF_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_HBUF_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_HBUF_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO1 14:14 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO1_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO1_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO1_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO2 15:15 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO2_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO2_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO2_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_ADR 16:16 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_ADR_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_ADR_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_ADR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_ADR 17:17 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_ADR_FALSE 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_ADR_TRUE 0x1 /* R---V */ +#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_ADR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR 0x00000E30 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_CMPL_DBUF 0:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_CMPL_DBUF_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_CMPL_HBUF 1:1 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_CMPL_HBUF_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY 2:2 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY_SEQID0 3:3 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY_SEQID0_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY_SEQID1 4:4 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY_SEQID1_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_DBUF 5:5 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_DBUF_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF 6:6 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_NP_LEN 7:7 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_NP_LEN_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_PW_LEN 8:8 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_PW_LEN_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_UCFIFO 9:9 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_UCFIFO_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_TXTF_FIFO1 10:10 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_TXTF_FIFO1_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_TXTF_FIFO2 11:11 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_TXTF_FIFO2_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_DBUF0 12:12 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_DBUF0_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_DBUF1 13:13 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_DBUF1_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_HBUF 14:14 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_HBUF_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_DBUF_ADR 16:16 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_DBUF_ADR_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF_ADR 17:17 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF_ADR_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF0 18:18 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF0_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRBS 0x00000E34 /* R--4R */ +#define NV_PROJ__PCIE2_RP_PRBS_ERR_COUNT_OVERFLOW 15:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_PRBS_LOCKED 31:16 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LANE_PRBS_ERR 0x00000E38 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_LANE_PRBS_ERR_SELECT 3:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_LANE_PRBS_ERR_SELECT_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LANE_PRBS_ERR_COUNT 31:16 /* R--VF */ +#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_0 0x00000E3C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_0_L0_LPBK 15:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_0_L0_LPBK_INIT 0x80 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_0_RCVRCFG_SUC_SPEED 31:16 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_0_RCVRCFG_SUC_SPEED_INIT 0x500 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_1 0x00000E40 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_1_UNSUC_SPEED_GEN1 15:0 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_1_UNSUC_SPEED_GEN1_INIT 0x7D0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_1_UNSUC_SPEED_GEN2 31:16 /* RWIUF */ +#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_1_UNSUC_SPEED_GEN2_INIT 0x3E80 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG 0x00000E44 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM0 0:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM0_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM0_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM1 1:1 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM1_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM1_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM2 2:2 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM2_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM2_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM3 3:3 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM3_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM3_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM4 4:4 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM4_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM4_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM5 5:5 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM5_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM5_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM6 6:6 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM6_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM6_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM7 7:7 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM7_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM7_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM8 8:8 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM8_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM8_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM9 9:9 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM9_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM9_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM10 10:10 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM10_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM10_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM11 11:11 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM11_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM11_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM12 12:12 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM12_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM12_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM13 13:13 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM13_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM13_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM14 14:14 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM14_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM14_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM15 15:15 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM15_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM15_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM16 16:16 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM16_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM16_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM17 17:17 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM17_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM17_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM18 18:18 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM18_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM18_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM19 19:19 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM19_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM19_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM20 20:20 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM20_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM20_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM21 21:21 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM21_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM21_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM22 22:22 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM22_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM22_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM23 23:23 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM23_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM23_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM24 24:24 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM24_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM24_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM25 25:25 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM25_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM25_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM26 26:26 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM26_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM26_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM27 27:27 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM27_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM27_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM28 28:28 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM28_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM28_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM29 29:29 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM29_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM29_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM30 30:30 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM30_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM30_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM31 31:31 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM31_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM31_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS 0x00000E48 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_LCRC_ERR 0:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_LCRC_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_LCRC_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_FRAMING_ERR 1:1 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_FRAMING_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_FRAMING_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_HDR_ERR 2:2 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_HDR_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_HDR_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_HDR_ERR 3:3 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_HDR_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_HDR_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_HDR_ERR 4:4 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_HDR_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_HDR_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_DATA_ERR 5:5 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_DATA_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_DATA_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_DATA_ERR 6:6 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_DATA_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_DATA_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_DATA_ERR 7:7 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_DATA_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_DATA_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISONP_HDR_ERR 8:8 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISONP_HDR_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISONP_HDR_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_HDR_ERR 9:9 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_HDR_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_HDR_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_DATA_ERR 10:10 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_DATA_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_DATA_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_TOO_MANY_CREDITS_ERR 11:11 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_TOO_MANY_CREDITS_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_TOO_MANY_CREDITS_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_UPDATE_FC_ERR 12:12 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_UPDATE_FC_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_UPDATE_FC_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_TOO_MANY_CREDITS_ERR 13:13 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_TOO_MANY_CREDITS_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_TOO_MANY_CREDITS_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_UPDATE_FC_ERR 14:14 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_UPDATE_FC_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_UPDATE_FC_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_TOO_MANY_CREDITS_ERR 15:15 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_TOO_MANY_CREDITS_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_TOO_MANY_CREDITS_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_UPDATE_FC_ERR 16:16 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_UPDATE_FC_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_UPDATE_FC_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_TOO_MANY_CREDITS_ERR 17:17 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_TOO_MANY_CREDITS_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_TOO_MANY_CREDITS_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_UPDATE_FC_ERR 18:18 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_UPDATE_FC_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_UPDATE_FC_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_TOO_MANY_CREDITS_ERR 19:19 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_TOO_MANY_CREDITS_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_TOO_MANY_CREDITS_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_UPDATE_FC_ERR 20:20 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_UPDATE_FC_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_UPDATE_FC_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_TOO_MANY_CREDITS_ERR 21:21 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_TOO_MANY_CREDITS_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_TOO_MANY_CREDITS_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_UPDATE_FC_ERR 22:22 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_UPDATE_FC_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_UPDATE_FC_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_ROLLOVER_ERR 23:23 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_ROLLOVER_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_ROLLOVER_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_STARTED_ERR 24:24 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_STARTED_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_STARTED_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_8B10B_ERR 25:25 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_8B10B_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_8B10B_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DLLP_CRC_ERR 26:26 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DLLP_CRC_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DLLP_CRC_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_TRAINING_ERR 27:27 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_TRAINING_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_TRAINING_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DESKEW_ERR 28:28 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DESKEW_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DESKEW_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_SA_ERR 29:29 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_SA_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_SA_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_TIMER_EXPIRED_ERR 30:30 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_TIMER_EXPIRED_ERR_INIT 0x0 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_TIMER_EXPIRED_ERR_CLEAR 0x1 /* -W--C */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL 0x00000E4C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_STORE_EN 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_STORE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_STORE_EN_CLEAR 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_STORE_EN_SET 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_WRAP_EN 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_WRAP_EN_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_WRAP_EN_CLEAR 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_WRAP_EN_SET 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_CLEAR_RAM 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_CLEAR_RAM_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_ON_EVENT 3:3 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_ON_EVENT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_LTSSM_MAJOR 7:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_LTSSM_MAJOR_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_PTX_LTSSM_MINOR 10:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_PTX_LTSSM_MINOR_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_PRX_LTSSM_MINOR 13:11 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_PRX_LTSSM_MINOR_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS 0x00000E50 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_RAM_FULL 0:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_WRITE_PTR 5:1 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_READ_ADDR 10:6 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_READ_ADDR_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_READ_DATA_VALID 11:11 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_LTSSM_MAJOR 15:12 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_PTX_LTSSM_MINOR 18:16 /* R--VF */ +#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_PRX_LTSSM_MINOR 21:19 /* R--VF */ +#define NV_PROJ__PCIE2_RP_VEND_XP 0x00000F00 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP_EMULATION 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_EMULATION_OFF 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_EMULATION_ON 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PRBS_EN 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PRBS_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PRBS_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PRBS_STAT 17:2 /* R--VF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_UPDATE_FC_THRESHOLD 25:18 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_UPDATE_FC_THRESHOLD_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_UPDATE_FC_THRESHOLD__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_TRAIN_ERR_ENABLE 26:26 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_TRAIN_ERR_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_TRAIN_ERR_ENABLE__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_ACK 27:27 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_ACK_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_ACK__PROD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_UPDATEFC 28:28 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_UPDATEFC_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_UPDATEFC__PROD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_INTERLEAVE_DLLPS 29:29 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_INTERLEAVE_DLLPS_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_INTERLEAVE_DLLPS__PROD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_DL_UP 30:30 /* R--VF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_FORCE_COMPLIANCE 31:31 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_FORCE_COMPLIANCE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1 0x00000F04 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_MAXWIDTH 5:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_MAXWIDTH_INIT 0x000000010 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_GEN2_LINK_UPGRADE 6:6 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_GEN2_LINK_UPGRADE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_EN 7:7 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_EN_ZERO 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_GEN2_WAIT_FOR_FIRST_EIES 8:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_GEN2_WAIT_FOR_FIRST_EIES_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_ACK_TIMER_LIMIT 18:10 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_ACK_TIMER_LIMIT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_ACK_TIMER_LIMIT__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_CYA 26:19 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_CYA_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_CYA__PROD 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_FORCE_UPSTREAM_NONCOH 27:27 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_FORCE_UPSTREAM_NONCOH_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_FORCE_UPSTREAM_NONCOH_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP1_FORCE_UPSTREAM_NONCOH_DISABLED 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP2 0x00000F08 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_ACK_WAKE 7:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_ACK_WAKE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_ACK_WAKE__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_THRESHOLD 17:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_THRESHOLD_INIT 0x000003FF /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_THRESHOLD__PROD 0x000003FF /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_THRESHOLD_REMOTE_NFTS 0x000003FF /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_UPDATE_WAKE 31:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_UPDATE_WAKE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_UPDATE_WAKE__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT 0x00000F0C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND 9:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_DEFAULT 0x000000FA /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_250 0x000000FA /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_278 0x00000116 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_313 0x00000139 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_357 0x00000165 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_417 0x000001A1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_500 0x000001F4 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_555 0x0000022B /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND__PROD_C_FPGA 0x000000FA /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_100MS_DFPCI 31:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_100MS_DFPCI_333 0x00000030 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_100MS_DFPCI_250 0x00000018 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_100MS_DFPCI__PROD 0x00000018 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_CMN 0x00000F14 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XV_CMN_ISO2TC_MAP 31:29 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XV_CMN_ISO2TC_MAP_7 0x00000007 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XV_CMN_ISO2TC_MAP__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT 0x00000F18 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_ENABLE 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_ENABLE_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_DUTY_CYCLE 3:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_DUTY_CYCLE_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_PERIOD 15:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_PERIOD_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP 0x00000F20 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_BUTTON_PRESENT 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_BUTTON_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_BUTTON_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_CONTROLLER_PRESENT 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_CONTROLLER_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_CONTROLLER_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_MRL_SENSOR_PRESENT 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_MRL_SENSOR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_MRL_SENSOR_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_INDICATOR_PRESENT 3:3 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_INDICATOR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_INDICATOR_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_INDICATOR_PRESENT 4:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_INDICATOR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_INDICATOR_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_SURPRISE 5:5 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_SURPRISE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_SURPRISE__PROD_C_HPC 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_CAPABLE 6:6 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_CAPABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_CAPABLE__PROD_C_HPC 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_VALUE 14:7 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_VALUE__PROD_C 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_SCALE 16:15 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_SCALE__PROD_C 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ELECTROMECH_INTERLOCK_PRESENT 17:17 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ELECTROMECH_INTERLOCK_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ELECTROMECH_INTERLOCK_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_NO_CMD_COMPLETED_SUPPORT 18:18 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_NO_CMD_COMPLETED_SUPPORT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_NO_CMD_COMPLETED_SUPPORT__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_PHYSICAL_SLOT_NUMBER 31:19 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_PHYSICAL_SLOT_NUMBER_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_PHYSICAL_SLOT_NUMBER__PROD_C 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0 0x00000F44 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_PASSPW_RO 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_PASSPW_RO_NOT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_PASSPW_RO__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_PASSPW_RO_YES 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_GPU_NISONC2HPISO 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_GPU_NISONC2HPISO_EN 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_GPU_NISONC2HPISO__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_GPU_NISONC2HPISO_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_DFPCI_ERR 3:3 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_DFPCI_ERR_NO 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_DFPCI_ERR_YES 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_DFPCI_ERR__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_IGNORE_BME 4:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_IGNORE_BME_NO 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_IGNORE_BME__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_IGNORE_BME_YES 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_ADR64 5:5 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_ADR64_EN 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_ADR64__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_ADR64_DIS 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_MAX_PAYLOAD_SIZE 8:6 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_MAX_PAYLOAD_SIZE_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_MAX_PAYLOAD_SIZE_4KB 0x00000005 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_MAX_PAYLOAD_SIZE_AUTO 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_ALL_MODE 9:9 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_ALL_MODE_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_ALL_MODE_YES 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_ALL_MODE_NO 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_UR_PW_DROP_ALL_MODE 10:10 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_UR_PW_DROP_ALL_MODE_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_UR_PW_DROP_ALL_MODE_YES 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_UR_PW_DROP_ALL_MODE_NO 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_FINISH_PKT_ON_RCVRY_EN 11:11 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_FINISH_PKT_ON_RCVRY_EN_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DSK_RESET_PULSE_WIDTH 15:12 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DSK_RESET_PULSE_WIDTH_INIT 0x00000008 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_NATIVE_P2P_STARVE_COUNT 23:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_NATIVE_P2P_STARVE_COUNT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_NATIVE_P2P_STARVE_COUNT__PROD 0x00000004 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_UP_NC2C 29:29 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_UP_NC2C_EN 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_UP_NC2C__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_UP_NC2C_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_FORCE_RETRY_POSSIBLE 30:30 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_FORCE_RETRY_POSSIBLE_NO 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_FORCE_RETRY_POSSIBLE_YES 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DISABLE_CRS 31:31 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DISABLE_CRS_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA0_DISABLE_CRS__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1 0x00000F48 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_BLOCK_P2P_ONLY 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_BLOCK_P2P_ONLY_EN 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_BLOCK_P2P_ONLY__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_BLOCK_P2P_ONLY_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_TC2ISO_MAP 3:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_TC2ISO_MAP_7 0x00000007 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_TC2ISO_MAP__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_ACCEPT_MSGD1 4:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_ACCEPT_MSGD1_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_ACCEPT_MSGD1_EN 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_ACCEPT_MSGD1__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSI_CAP 12:12 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSI_CAP_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSI_CAP_EN 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSI_CAP__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_ERPT 13:13 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_ERPT_EN 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_ERPT_DIS 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_ERPT__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_ISO2NISO 14:14 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_ISO2NISO_EN 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_ISO2NISO_DIS 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_ISO2NISO__PROD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_LINKACTV_REPORTING 15:15 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_LINKACTV_REPORTING_CAPABLE 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_LINKACTV_REPORTING_NOT_CAPABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_LINKACTV_REPORTING__PROD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSIMAP 16:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSIMAP_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSIMAP_EN 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSIMAP__PROD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST 0x00000F4C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL 31:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL__PROD 0x10000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN 0x00000F50 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1_EN 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1_DIS 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1__PROD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC_EN 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC__PROD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED_EN 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED_DIS 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED__PROD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1 4:3 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L0 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1P 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1PP 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC 6:5 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L0 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1P 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1PP 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC__PROD 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MINIMUM 14:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MINIMUM_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND 25:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_DEFAULT 0x000000FA /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_278 0x00000116 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_312 0x00000138 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_333 0x0000014D /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_357 0x00000165 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_417 0x000001A1 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_500 0x000001F4 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_555 0x0000022B /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_XVR_USE_DFPCI_DATA_UNINTR 26:26 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_XVR_USE_DFPCI_DATA_UNINTR_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_XVR_USE_DFPCI_DATA_UNINTR__PROD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_FTS 0x00000F54 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_N_FTS 7:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_N_FTS_INIT 0x0000001F /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_N_FTS__PROD 0x0000001F /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_N_FTS_REMOTE 15:8 /* R--VF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_DETECT_START 25:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_DETECT_START_INIT 0x00000040 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_DETECT_START__PROD 0x00000040 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0 0x00000F58 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_8B10B_ERRORS_LC 0:0 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_8B10B_ERRORS_LC_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_8B10B_ERRORS_INF 4:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_8B10B_ERRORS_INF_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_CRC_ERRORS_LC 8:8 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_CRC_ERRORS_LC_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_CRC_ERRORS_INF 12:12 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_CRC_ERRORS_INF_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_NAKS_RCVD_LC 16:16 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_NAKS_RCVD_LC_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_NAKS_RCVD_INF 20:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_NAKS_RCVD_INF_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_FAILED_L0S_EXITS_LC 24:24 /* C-IVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_FAILED_L0S_EXITS_LC_INIT 0x00000000 /* C-I-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_FAILED_L0S_EXITS_INF 28:28 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_FAILED_L0S_EXITS_INF_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS1 0x00000F5C /* R--4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS1_8B10B_ERRORS 7:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS1_CRC_ERRORS 15:8 /* R--VF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS1_NAKS_RCVD 23:16 /* R--VF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_STATS1_FAILED_L0S_EXITS 31:24 /* R--VF */ +#define NV_PROJ__PCIE2_RP_VEND_ERROR_COUNT 0x00000F60 /* R--4R */ +#define NV_PROJ__PCIE2_RP_VEND_ERROR_COUNT_LCRC_ERR 7:0 /* R--VF */ +#define NV_PROJ__PCIE2_RP_VEND_ERROR_COUNT_BAD_TLP 15:8 /* R--VF */ +#define NV_PROJ__PCIE2_RP_VEND_ERROR_COUNT_REPLAY 23:16 /* R--VF */ +#define NV_PROJ__PCIE2_RP_CFG_MISC 0x00000F64 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_CFG_MISC_MUTE_IDLE 7:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_CFG_MISC_MUTE_IDLE_MIN 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CFG_MISC_MUTE_IDLE_MAX 0x000000FF /* RW--V */ +#define NV_PROJ__PCIE2_RP_CFG_MISC_MUTE_IDLE__PROD 0x0000001F /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY 0x00000F68 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_THRESHOLD 19:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_THRESHOLD_2500 0x000009C4 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_WINDOW 30:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_WINDOW_100US 0x00000064 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_ENABLE 31:31 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2 0x00000F6C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_SPEED_CHANGE 0:0 /* CWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_SPEED_CHANGE_ZERO 0x00000000 /* CWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ADVERTISED_RATE_CHANGE 1:1 /* CWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ADVERTISED_RATE_CHANGE_ZERO 0x00000000 /* CWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_TX_MARGIN_OVERRIDE 3:3 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_TX_MARGIN_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_TX_MARGIN_OVERRIDE_ENABLED 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED 7:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED_2P5 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED_5P0 0x00000002 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED 11:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_2P5 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_5P0_2P5 0x00000002 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE 15:12 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_2P5 0x00000001 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_5P0_2P5 0x00000002 /* R---V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_AUTONOMOUS_CHANGE 16:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_AUTONOMOUS_CHANGE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_POLLING_PREDETERMINED_LANES 17:17 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_POLLING_PREDETERMINED_LANES_DISABLE 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ENFORCE_DEEMPHASIS 18:18 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ENFORCE_DEEMPHASIS_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DEEMPHASIS_STRAP 19:19 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DEEMPHASIS_STRAP_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_N_EIE_SYMBOLS 23:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_N_EIE_SYMBOLS_INIT 0x00000006 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_RECOVERY_SPEED_TIMEOUT_ADJ 26:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_RECOVERY_SPEED_TIMEOUT_ADJ_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ALLOW_SPEED_CHANGE_FROM_L1 27:27 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ALLOW_SPEED_CHANGE_FROM_L1_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_SURPRISE_IDLE_USE_STAT_IDLE 28:28 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_SURPRISE_IDLE_USE_STAT_IDLE_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_EIDLE_INFERENCE_EN 29:29 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_EIDLE_INFERENCE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_REV2P0_COMPLIANCE_DIS 30:30 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_REV2P0_COMPLIANCE_DIS_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_REV2P0_COMPLIANCE_DIS__PROD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_UPCONFIGURE_CAPABLE 31:31 /* R--VF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_PAD_PWRUP 0x00000F74 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_PAD_PWRUP_PMRX_PWRUP_THRESHOLD 23:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_PAD_PWRUP_PMRX_PWRUP_THRESHOLD_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_GEN2_PAD_PWRDN 0x00000F78 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_GEN2_PAD_PWRDN_MICROSECOND 25:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_GEN2_PAD_PWRDN_MICROSECOND_277 0x00000115 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_GEN2_PAD_PWRDN_MICROSECOND_555 0x0000022B /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_GEN2_PAD_PWRDN_MICROSECOND_500 0x000001F4 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_REASONS 0x00000F84 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_REASONS_VALUE 31:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_REASONS_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_REASONS_VALUE_REC_ALL 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_REASONS_VALUE_REC_NEXT 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_COUNT 0x00000F88 /* R--4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_COUNT_VALUE 31:0 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2 0x00000F8C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_DIS_MA_TA_EP_MERGE 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_DIS_MA_TA_EP_MERGE_ON 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_DIS_MA_TA_EP_MERGE_OFF 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_DEV_CAP_EXTENDED_TAG_FIELD_SIZE 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_DEV_CAP_EXTENDED_TAG_FIELD_SIZE_8B 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_DEV_CAP_EXTENDED_TAG_FIELD_SIZE_5B 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_PROTOCOL_DISABLE 4:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_PROTOCOL_DISABLE_OFF 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_PROTOCOL_DISABLE_ON 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_SPEED_DISABLE 5:5 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_SPEED_DISABLE_ON 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_SPEED_DISABLE_OFF 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_PCA_ENABLE 7:7 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_PCA_ENABLE_ON 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_PCA_ENABLE_OFF 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_NMI 8:8 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_NMI_FALSE 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_NMI_TRUE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_NMI_CLEAR 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_PME 9:9 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_PME_FALSE 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_PME_TRUE 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_PME_CLEAR 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_SLOT_IMPLEMENTED 11:11 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_SLOT_IMPLEMENTED_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_SLOT_IMPLEMENTED_YES 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_SLOT_IMPLEMENTED_NO 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_FUSE_GEN2_PROTOCOL_DISABLE 12:12 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_FUSE_GEN2_PROTOCOL_DISABLE_ON 0x00000001 /* R---V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_FUSE_GEN2_PROTOCOL_DISABLE_OFF 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_SHADOW_LINK_BW_NOTIFY_CAP 13:13 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_SHADOW_LINK_BW_NOTIFY_CAP_EN 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_SHADOW_LINK_BW_NOTIFY_CAP_DIS 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_DIS 16:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_DIS_TRUE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_DIS_FALSE 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_DIS 17:17 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_DIS_TRUE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_DIS_FALSE 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_INT_EN_DIS 18:18 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_INT_EN_DIS_TRUE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_INT_EN_DIS_FALSE 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_INT_EN_DIS 19:19 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_INT_EN_DIS_TRUE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_INT_EN_DIS_FALSE 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_HW_AUTO_WIDTH_DISABLE_DIS 20:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_HW_AUTO_WIDTH_DISABLE_DIS_TRUE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_HW_AUTO_WIDTH_DISABLE_DIS_FALSE 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_BLOCK_UP_TRANSACTIONS_ON_ERR 21:21 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_BLOCK_UP_TRANSACTIONS_ON_ERR_EN 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_BLOCK_UP_TRANSACTIONS_ON_ERR_DIS 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_UNBLOCK_UP_TRANSACTIONS 22:22 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_UNBLOCK_UP_TRANSACTIONS_FALSE 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_UNBLOCK_UP_TRANSACTIONS_TRUE 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_IGNORE_ATTENTION_BUTTON_MSG 23:23 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_IGNORE_ATTENTION_BUTTON_MSG_FALSE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_IGNORE_ATTENTION_BUTTON_MSG_TRUE 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_COMPLIANCE_X8_DELAY 24:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_CYA2_COMPLIANCE_X8_DELAY_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG 0x00000F94 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION 1:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION_TX_L0S 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION_RX_L0S 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION_L1 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION_IDLE 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DURATION_IN_LOW_PWR_100NS 0x00000F98 /* R-I4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DURATION_IN_LOW_PWR_100NS_VALUE 31:0 /* R-IVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_DURATION_IN_LOW_PWR_100NS_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT 0x00000F9C /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD 12:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_INIT 0x00000569 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_250 0x000004E2 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_278 0x00000569 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_313 0x0000061A /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_357 0x000006F5 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_417 0x00000821 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_500 0x000009BF /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_555 0x00000AD2 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2 25:13 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_INIT 0x00000569 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_250 0x00000271 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_278 0x000002B4 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_313 0x0000030D /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_357 0x0000037A /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_417 0x00000410 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_500 0x000004DF /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_555 0x00000569 /* RW--V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_EIDLE_INFERENCE_TIMEOUT 0x00000FA0 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_EIDLE_INFERENCE_TIMEOUT_A 15:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_EIDLE_INFERENCE_TIMEOUT_A_INIT 0x0000008F /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_EIDLE_INFERENCE_TIMEOUT_B 31:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_XP_EIDLE_INFERENCE_TIMEOUT_B_INIT 0x000006F2 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC 0x00000FA4 /* RWI4R */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_COMMAND 31:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_COMMAND_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE 15:8 /* R--VF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE7 7:7 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE7_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE7_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE6 6:6 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE6_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE6_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE5 5:5 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE5_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE5_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE4 4:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE4_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE4_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE3 3:3 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE3_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE3_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE2 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE2_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE2_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE1 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE1_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE1_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE0 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE0_INIT 0x00000000 /* R-I-V */ +#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE0_SET 0x00000001 /* -W--C */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0 0x00000FA8 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_0 3:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_0_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_1 7:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_1_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_2 11:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_2_INIT 0x00000002 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_3 15:12 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_3_INIT 0x00000003 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_4 19:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_4_INIT 0x00000004 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_5 23:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_5_INIT 0x00000005 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_6 27:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_6_INIT 0x00000006 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_7 31:28 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_7_INIT 0x00000007 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1 0x00000FAC /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_8 3:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_8_INIT 0x00000008 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_9 7:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_9_INIT 0x00000009 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_10 11:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_10_INIT 0x0000000A /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_11 15:12 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_11_INIT 0x0000000B /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_12 19:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_12_INIT 0x0000000C /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_13 23:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_13_INIT 0x0000000D /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_14 27:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_14_INIT 0x0000000E /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_15 31:28 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_15_INIT 0x0000000F /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SHADOW_SS_1 0x00000FB0 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_SHADOW_SS_1_SSID 31:16 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_VEND_SHADOW_SS_1_SSID_INIT 0x0 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_SHADOW_SS_1_SSVID 15:0 /* RWCVF */ +#define NV_PROJ__PCIE2_RP_VEND_SHADOW_SS_1_SSVID_INIT 0x10DE /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP 0x00000FB4 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE0 5:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE0_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE1 13:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE1_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE2 21:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE2_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE3 29:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE3_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP 0x00000FB8 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE4 5:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE4_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE5 13:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE5_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE6 21:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE6_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE7 29:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE7_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CTL_2 0x00000FBC /* RW-4R */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R0_1C 18:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R0_1C_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R0_1C_NO_EQ 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R0_1C_MAX_EQ 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R1_1C 22:20 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R1_1C_DEFAULT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R1_1C_NO_EQ 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R1_1C_MAX_EQ 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R2_1C 26:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R2_1C_DEFAULT 0x00000003 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R2_1C_NO_EQ 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R2_1C_MAX_EQ 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3 0x00000FC0 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C 5:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C_DEFAULT 0x0000000C /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C_1150_MVPPD 0x0000000F /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C_1100_MVPPD 0x0000000E /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C_1050_MVPPD 0x0000000D /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C_1000_MVPPD 0x0000000C /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__950_MVPPD 0x0000000B /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__900_MVPPD 0x0000000A /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__850_MVPPD 0x00000009 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__800_MVPPD 0x00000008 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__750_MVPPD 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__700_MVPPD 0x00000006 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__650_MVPPD 0x00000005 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__600_MVPPD 0x00000004 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__550_MVPPD 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__500_MVPPD 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__450_MVPPD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__400_MVPPD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C 12:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C_DEFAULT 0x0000000A /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C_MAX 0x0000000F /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C_36DB 0x0000000A /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C_6DB 0x0000000F /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C 21:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C_DEFAULT 0x0000000C /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C_1150_MVPPD 0x0000000F /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C_1100_MVPPD 0x0000000E /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C_1050_MVPPD 0x0000000D /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C_1000_MVPPD 0x0000000C /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__950_MVPPD 0x0000000B /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__900_MVPPD 0x0000000A /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__850_MVPPD 0x00000009 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__800_MVPPD 0x00000008 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__750_MVPPD 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__700_MVPPD 0x00000006 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__650_MVPPD 0x00000005 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__600_MVPPD 0x00000004 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__550_MVPPD 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__500_MVPPD 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__450_MVPPD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__400_MVPPD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C 27:23 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C_DEFAULT 0x0000000A /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C_MAX 0x0000000F /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C_36DB 0x0000000A /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C_6DB 0x0000000F /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4 0x00000FC4 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C 5:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C_DEFAULT 0x0000000C /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C_1150_MVPPD 0x0000000F /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C_1100_MVPPD 0x0000000E /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C_1050_MVPPD 0x0000000D /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C_1000_MVPPD 0x0000000C /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__950_MVPPD 0x0000000B /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__900_MVPPD 0x0000000A /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__850_MVPPD 0x00000009 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__800_MVPPD 0x00000008 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__750_MVPPD 0x00000007 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__700_MVPPD 0x00000006 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__650_MVPPD 0x00000005 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__600_MVPPD 0x00000004 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__550_MVPPD 0x00000003 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__500_MVPPD 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__450_MVPPD 0x00000001 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__400_MVPPD 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C 12:8 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C_DEFAULT 0x0000000F /* RWI-V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C_MAX 0x0000000F /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C_DISABLE 0x00000000 /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C_36DB 0x0000000A /* RW--V */ +#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C_6DB 0x0000000F /* RW--V */ +#define NV_PROJ__PCIE2_RP_TIMEOUT2 0x00000FC8 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_TIMEOUT2_MIN_L1_L2_IDLE_TIME 4:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_TIMEOUT2_MIN_L1_L2_IDLE_TIME_INIT 0x0000000A /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC 0x00000FCC /* RW-4R */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC_PRSNT_MAP 3:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC_PRSNT_MAP_INIT 0x0000000F /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD 22:16 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_INIT 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE 23:23 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD 30:24 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_INIT 0x00000003 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE 31:31 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2 0x00000FD0 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_SHORT_LINK_TIMERS 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_SHORT_LINK_TIMERS_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_EIDLE_ENTRY 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_EIDLE_ENTRY_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_EIDLE_EXIT 2:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_EIDLE_EXIT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_MIN_EIDLE 3:3 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_MIN_EIDLE_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_SPEED 7:4 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_SPEED_2P5 0x00000001 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_SPEED_5P0 0x00000002 /* RW--V */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_OVERRIDE_JTAG 31:31 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_OVERRIDE_JTAG_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_VEND_XP3 0x00000FD4 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_VEND_XP3_SA_ERROR_LIMIT 7:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_VEND_XP3_SA_ERROR_LIMIT_INIT 0x00000003 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1 0x00000FD8 /* RW-4R */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1_FORCE_SA_IN_CONFIG 0:0 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1_FORCE_SA_IN_CONFIG_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1_LWLO_HUNT_ON_BAD_TS1 1:1 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1_LWLO_HUNT_ON_BAD_TS1_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1_IDLE_TO_L0_DELAY 5:2 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1_IDLE_TO_L0_DELAY_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1_RESET_LANE_ENABLE_ORIG_IN_DETECT 6:6 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1_RESET_LANE_ENABLE_ORIG_IN_DETECT_INIT 0x00000000 /* RWI-V */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1_SPARE 31:7 /* RWIVF */ +#define NV_PROJ__PCIE2_RP_XP_CYA_1_SPARE_INIT 0x00000000 /* RWI-V */ + +#endif // ___DEV_AP_PCIE2_ROOT_PORT_H_INC_ + diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h index 6014edf60d93..c5cbd3e63910 100644 --- a/arch/arm/mach-tegra/include/mach/hardware.h +++ b/arch/arm/mach-tegra/include/mach/hardware.h @@ -21,4 +21,8 @@ #ifndef __MACH_TEGRA_HARDWARE_H #define __MACH_TEGRA_HARDWARE_H +#define pcibios_assign_all_busses() 0 +#define PCIBIOS_MIN_IO 0x83000000ul +#define PCIBIOS_MIN_MEM 0x90000000ul + #endif diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index 89cfa2a4b027..c540a10f7b67 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -194,6 +194,9 @@ #define TEGRA_CSITE_BASE 0x70040000 #define TEGRA_CSITE_SIZE SZ_256K +#define TEGRA_PCIE_BASE 0x80000000 +#define TEGRA_PCIE_SIZE SZ_1G + #define TEGRA_USB_BASE 0xC5000000 #define TEGRA_USB_SIZE SZ_16K diff --git a/arch/arm/mach-tegra/include/mach/pci.h b/arch/arm/mach-tegra/include/mach/pci.h new file mode 100644 index 000000000000..196cdb8fa900 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/pci.h @@ -0,0 +1,337 @@ +/* + * arch/arm/mach-tegra/include/mach/pci.h + * + * Header file containing constants for the tegra PCIe driver. + * + * Copyright (c) 2008-2009, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __MACH_TEGRA_PCI_H + +#include <linux/pci.h> + +#include "nvrm_drf.h" +#include "ap20/dev_ap_pcie2_root_port.h" +#include "ap20/dev_ap_pcie2_pads.h" +#include "ap20/arafi.h" + +extern void __iomem * volatile pci_tegra_regs; + +/* + * AXI address map for the PCIe aperture. AP20, defines 1GB in the AXI + * address map for PCIe. + * + * That address space is split into different regions, with sizes and + * offsets as follows. Exepct for the Register space, SW is free to slice the + * regions as it chooces. + * + * The split below seems to work fine for now. + * + * 0x8000_0000 to 0x80ff_ffff - Register space 16MB. + * 0x8100_0000 to 0x81ff_ffff - Config space 16MB. + * 0x8200_0000 to 0x82ff_ffff - Extended config space 16MB. + * 0x8300_0000 to 0x83ff_ffff - Downstream IO space + * ... Will be filled with other BARS like MSI/upstream IO etc. + * 0x9000_0000 to 0x9fff_ffff - non-prefetchable memory aperture + * 0xa000_0000 to 0xbfff_ffff - Prefetchable memory aperture + * + * Config and Extended config sizes are choosen to support + * maximum of 256 devices, + * which is good enough for all the AP20 use cases. + * */ + +#define PCIE_REGS_SIZE 0x01000000UL +#define PCIE_CONFIG_OFFSET PCIE_REGS_SIZE +#define PCIE_CONFIG_SIZE 0x01000000UL +#define PCIE_EXTENDED_CONFIG_OFFSET (PCIE_CONFIG_SIZE + PCIE_CONFIG_OFFSET) +#define PCIE_EXTENDED_CONFIG_SIZE 0x01000000UL +#define PCIE_DOWNSTREAM_IO_OFFSET (PCIE_EXTENDED_CONFIG_SIZE + \ + PCIE_EXTENDED_CONFIG_OFFSET) +#define PCIE_DOWNSTREAM_IO_SIZE 0x00100000UL + +#define PCIE_NON_PREFETCH_MEMORY_OFFSET 0x10000000UL +#define PCIE_NON_PREFETCH_MEMORY_SIZE 0x10000000UL +#define PCIE_PREFETCH_MEMORY_OFFSET (PCIE_NON_PREFETCH_MEMORY_OFFSET + \ + PCIE_NON_PREFETCH_MEMORY_SIZE) +#define PCIE_PREFETCH_MEMORY_SIZE 0x20000000UL + +/* PCIe registers can be classified into 4 regions. + * + * 1. AFI registers - AFI is a wrapper between PCIE and ARM AXI bus. These + * registers define the address translation registers, interrupt registers and + * some configuration (a.k.a CYA) registers. + * 2. PAD registers - PAD control registers which are inside the PCIE CORE. + * 3. Configuration 0 and Configuration 1 registers - These registers are PCIe + * configuration registers of Root port 0 and root port 1. + * + * Check the PcieRegType enumeration for the list of Registers banks inside the + * PCIE aperture. + * + * */ +#define NV_PCIE_AXI_AFI_REGS_OFSET 0x3800UL +#define NV_PCIE_AXI_PADS_OFSET 0x3000UL +#define NV_PCIE_AXI_RP_T0C0_OFFSET 0x0000UL +#define NV_PCIE_AXI_RP_T0C1_OFFSET 0x1000UL + +/* During the boot only registers/config and extended config apertures are + * mapped. Rest are mapped on demand by the PCI device drivers. + */ +#define PCI_TEGRA_IOMAPPED_REG_APERTURE_SIZE \ + (PCIE_REGS_SIZE + PCIE_CONFIG_SIZE + PCIE_EXTENDED_CONFIG_SIZE) + +/* + * PCI address map for memory mapped devices. Still using 32-bit aperture. + * + * 1GB for the system memory. + * Everything mapped as cpu physical = pci + * + */ +#define FPCI_SYSTEM_MEMORY_OFFSET 0x0UL +#define FPCI_SYSTEM_MEMORY_SIZE 0x40000000UL +#define FPCI_NON_PREFETCH_MEMORY_OFFSET 0x90000000UL +#define FPCI_NON_PREFETCH_MEMORY_SIZE PCIE_NON_PREFETCH_MEMORY_SIZE +#define FPCI_PREFETCH_MEMORY_OFFSET (FPCI_NON_PREFETCH_MEMORY_OFFSET+ \ + FPCI_NON_PREFETCH_MEMORY_SIZE) +#define FPCI_PREFETCH_MEMORY_SIZE 0x40000000UL + + + + +/* PCIE DRF macros to read and write PRI registers */ + +/** NVPCIE_DRF_DEF - define a new register value. + + @param d register domain (hardware block) + @param r register name + @param f register field + @param c defined value for the field + */ +#define NVPCIE_DRF_DEF(d,r,f,c) \ + ((NV_PROJ__PCIE2_##d##_##r##_##f##_##c) \ + << NV_FIELD_SHIFT(NV_PROJ__PCIE2_##d##_##r##_##f)) + +/** NVPCIE_DRF_NUM - define a new register value. + + @param d register domain (hardware block) + @param r register name + @param f register field + @param n numeric value for the field + */ +#define NVPCIE_DRF_NUM(d,r,f,n) \ + (((n)& NV_FIELD_MASK(NV_PROJ__PCIE2_##d##_##r##_##f)) << \ + NV_FIELD_SHIFT(NV_PROJ__PCIE2_##d##_##r##_##f)) + +/** NVPCIE_DRF_VAL - read a field from a register. + + @param d register domain (hardware block) + @param r register name + @param f register field + @param v register value + */ +#define NVPCIE_DRF_VAL(d,r,f,v) \ + (((v)>> NV_FIELD_SHIFT(NV_PROJ__PCIE2_##d##_##r##_##f)) & \ + NV_FIELD_MASK(NV_PROJ__PCIE2_##d##_##r##_##f)) + +/** NVPCIE_FLD_SET_DRF_NUM - modify a register field. + + @param d register domain (hardware block) + @param r register name + @param f register field + @param n numeric field value + @param v register value + */ +#define NVPCIE_FLD_SET_DRF_NUM(d,r,f,n,v) \ + ((v & ~NV_FIELD_SHIFTMASK(NV_PROJ__PCIE2_##d##_##r##_##f)) | \ + NVPCIE_DRF_NUM(d,r,f,n)) + +/** NVPCIE_FLD_SET_DRF_DEF - modify a register field. + + @param d register domain (hardware block) + @param r register name + @param f register field + @param c defined field value + @param v register value + */ +#define NVPCIE_FLD_SET_DRF_DEF(d,r,f,c,v) \ + (((v) & ~NV_FIELD_SHIFTMASK(NV_PROJ__PCIE2_##d##_##r##_##f)) | \ + NVPCIE_DRF_DEF(d,r,f,c)) + +/** NVPCIE_RESETVAL - get the reset value for a register. + + @param d register domain (hardware block) + @param r register name + */ +#define NVPCIE_RESETVAL(d,r) (d##_##r##_0_RESET_VAL) + +/* Register access inline functions */ + +static inline void pci_tegra_afi_writel(u32 value,unsigned long offset) +{ + writel(value, offset + NV_PCIE_AXI_AFI_REGS_OFSET + pci_tegra_regs); +} + +static inline void pci_tegra_rp_writel(u32 value, unsigned long offset, int rp) +{ + BUG_ON(rp != 0 && rp != 1); + + if (rp == 0) offset += NV_PCIE_AXI_RP_T0C0_OFFSET; + if (rp == 1) offset += NV_PCIE_AXI_RP_T0C1_OFFSET; + + writel(value, offset + pci_tegra_regs); +} + +static inline void pci_tegra_rp_writew(u16 value, unsigned long offset, int rp) +{ + u32 reg; + + BUG_ON(rp != 0 && rp != 1); + + if (rp == 0) offset += NV_PCIE_AXI_RP_T0C0_OFFSET; + if (rp == 1) offset += NV_PCIE_AXI_RP_T0C1_OFFSET; + + reg = readl((offset & ~0x3) + pci_tegra_regs); + reg &= ~(0xffff << ((offset & 0x3) * 8)); + reg |= (u32)value << ((offset & 0x3) * 8); + writel(reg, (offset & ~0x3) + pci_tegra_regs); +} + +static inline void pci_tegra_rp_writeb(u8 value, unsigned long offset, int rp) +{ + u32 reg; + + BUG_ON(rp != 0 && rp != 1); + + if (rp == 0) offset += NV_PCIE_AXI_RP_T0C0_OFFSET; + if (rp == 1) offset += NV_PCIE_AXI_RP_T0C1_OFFSET; + + reg = readl((offset & ~0x3) + pci_tegra_regs); + reg &= ~(0xff << ((offset & 0x3) * 8)); + reg |= (u32)value << ((offset & 0x3) * 8); + writel(reg, (offset & ~0x3) + pci_tegra_regs); +} + +static inline void pci_tegra_pads_writel(u32 value, unsigned long offset) +{ + writel(value, offset + NV_PCIE_AXI_PADS_OFSET + pci_tegra_regs); +} + +static inline u32 pci_tegra_afi_readl(unsigned long offset) +{ + return readl(offset + NV_PCIE_AXI_AFI_REGS_OFSET + pci_tegra_regs); +} + +static inline u32 pci_tegra_rp_readl(unsigned long offset, int rp) +{ + BUG_ON(rp != 0 && rp != 1); + + if (rp == 0) offset += NV_PCIE_AXI_RP_T0C0_OFFSET; + if (rp == 1) offset += NV_PCIE_AXI_RP_T0C1_OFFSET; + + return readl(offset + pci_tegra_regs); +} + +static inline u16 pci_tegra_rp_readw(unsigned long offset, int rp) +{ + u32 val; + + BUG_ON(rp != 0 && rp != 1); + + if (rp == 0) offset += NV_PCIE_AXI_RP_T0C0_OFFSET; + if (rp == 1) offset += NV_PCIE_AXI_RP_T0C1_OFFSET; + + val = readl((offset & ~0x3) + pci_tegra_regs); + val >>= 8 * (offset & 3); + val &= 0xffff; + + return (u16)val; +} + +static inline u8 pci_tegra_rp_readb(unsigned long offset, int rp) +{ + u32 val; + + BUG_ON(rp != 0 && rp != 1); + + if (rp == 0) offset += NV_PCIE_AXI_RP_T0C0_OFFSET; + if (rp == 1) offset += NV_PCIE_AXI_RP_T0C1_OFFSET; + + val = readl((offset & ~0x3) + pci_tegra_regs); + val >>= 8 * (offset & 3); + val &= 0xff; + + return (u8)val; +} + +static inline u32 pci_tegra_pads_reedl(unsigned long offset) +{ + return readl(offset + NV_PCIE_AXI_PADS_OFSET + pci_tegra_regs); +} + +static inline bool pci_tegra_is_rp(u32 bus_number, int *rp) +{ + if (bus_number == pci_tegra_rp_readb(PCI_PRIMARY_BUS, 0)) { + *rp = 0; + return true; + } else if (bus_number == pci_tegra_rp_readb(PCI_PRIMARY_BUS, 1)) { + *rp = 1; + return true; + } else + return false; +} + +// return true if this is the first device on an (active) rootport +static inline bool pci_tegra_is_rp_first_dev(u32 bus_number, int rp) +{ + u8 primary, secondary; + + BUG_ON((rp != 0) && (rp != 1)); + + primary = pci_tegra_rp_readb(PCI_PRIMARY_BUS, rp); + secondary = pci_tegra_rp_readb(PCI_SECONDARY_BUS, rp); + if ((primary < secondary) && (bus_number == secondary)) + return true; + + return false; +} + +/* + * Given the bus number, devfn and the offset this API returns the mapped + * address of the config space. + */ +static inline void __iomem *pci_tegra_config_addr(u8 bus_number, + u32 devfn, u32 where) +{ + void *addr; + u32 function; + u32 device; + + function = PCI_FUNC(devfn); + device = PCI_SLOT(devfn); + + addr = pci_tegra_regs; + addr += (where < 256) ? PCIE_CONFIG_OFFSET + : PCIE_EXTENDED_CONFIG_OFFSET; + addr += bus_number << 16; + addr += device << 11; + addr += function << 8; + addr += where; + return addr; +} + +void pci_tegra_enumerate(void); + +#endif |