diff options
| author | Kaz Fukuoka <kfukuoka@nvidia.com> | 2011-05-25 18:21:32 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-22 23:29:01 -0700 |
| commit | 07ece5a59ef3394dcad439c727b1c8c3cb2d0b44 (patch) | |
| tree | b9b44fab961556334f0c73f900afefa07d001571 /arch/arm/mach-tegra/irq.c | |
| parent | fb57c5867e4a90d1849213636039a757fdc92bb2 (diff) | |
media: tegra: avp: Clear interrupt registers when AVP starts
There was no code to clear interrupt registers for AVP. First run
of AVP was OK because those registers start from reset value.
But because those registers were not cleared, when the second
time AVP was started, some interrupts were enabled too early.
That caused interrupts coming before handlers were ready.
This change also removes the workaroud for the bug.
bug 827353
bug 826234
Original-Change-Id: I51546400f0bace67dfcdb23f667c051c060d3983
Reviewed-on: http://git-master/r/33083
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: Re8d35d9a62267d2a66f7eb4e754651edafdbb536
Diffstat (limited to 'arch/arm/mach-tegra/irq.c')
| -rw-r--r-- | arch/arm/mach-tegra/irq.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index debbb7cc2a73..73a72618fa91 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -27,6 +27,7 @@ #include <asm/hardware/gic.h> #include <mach/iomap.h> +#include <mach/legacy_irq.h> #include "board.h" #include "pm-irq.h" @@ -212,3 +213,14 @@ void __init tegra_init_irq(void) gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); } + +void tegra_init_legacy_irq_cop(void) +{ + int i; + + for (i = 0; i < NUM_ICTLRS; i++) { + void __iomem *ictlr = ictlr_reg_base[i]; + writel(~0, ictlr + ICTLR_COP_IER_CLR); + writel(0, ictlr + ICTLR_COP_IEP_CLASS); + } +} |