diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-11-03 17:25:19 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-06-22 11:48:24 +0530 |
| commit | b18ec08e4ba25d8723fe80c9a541ca4caafe87f9 (patch) | |
| tree | 6ffbf162701fcd812f02cb085a3c58fb99c610f0 /arch/arm/mach-tegra/irq.c | |
| parent | 0af047ddb01572edb510ddd3f41761e2cc715003 (diff) | |
arm: tegra: Add support for Cortex-A15 GIC processor interface
The base address of the GIC processor interface is different on
Cortex-A15. Detect the processor type and use the corresponding
register base address.
Reviewed-on: http://git-master/r/62292
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Robert Bond <rbond@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
(cherry picked from commit 9940e233fe82bc47fe79265064d2a548a6a6515c)
Change-Id: I312eb22f99912e88a5ade9c86ac64aaf4309e651
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/77823
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Tested-by: Mark Stadler <mastadler@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/irq.c')
| -rw-r--r-- | arch/arm/mach-tegra/irq.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 12e42fe704e2..1aad5dcb06fb 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -198,10 +198,13 @@ subsys_initcall(tegra_legacy_irq_syscore_init); #define tegra_set_wake NULL #endif +void __iomem *tegra_gic_cpu_base; + void __init tegra_init_irq(void) { int i; void __iomem *distbase; + u32 midr; distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f; @@ -228,13 +231,19 @@ void __init tegra_init_irq(void) gic_arch_extn.irq_set_wake = tegra_set_wake; gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; + __asm__("mrc p15, 0, %0, c0, c0, 0\n" : "=r" (midr)); + + if ((midr & 0x0000FFF0) == 0x0000C090) + tegra_gic_cpu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100); + else + tegra_gic_cpu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x2000); + /* * Check if there is a devicetree present, since the GIC will be * initialized elsewhere under DT. */ if (!of_have_populated_dt()) - gic_init(0, 29, distbase, - IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); + gic_init(0, 29, distbase, tegra_gic_cpu_base); } void tegra_init_legacy_irq_cop(void) |