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| author | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-22 22:04:45 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-22 23:51:40 -0700 |
| commit | 9da975d1f7776c8a86e5a45a5ba5880f08d974d6 (patch) | |
| tree | f211ade482d22dc38cb8852ee4ec3a8373552ae0 /arch/arm/mach-tegra/latency_allowance.c | |
| parent | fec211bb5827ef1a4f27ac2b48ad5dafadbb1d6e (diff) | |
fixup don't cast __iomem pointers see 75d711662f02ad850f28507c0231cdce8fe075af
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/latency_allowance.c')
| -rw-r--r-- | arch/arm/mach-tegra/latency_allowance.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/latency_allowance.c b/arch/arm/mach-tegra/latency_allowance.c index 7698ba39f4ca..f46ea8f90cdc 100644 --- a/arch/arm/mach-tegra/latency_allowance.c +++ b/arch/arm/mach-tegra/latency_allowance.c @@ -122,9 +122,9 @@ static const int normal_atom_size = 16; static const int fdc_atom_size = 32; #define MC_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_MC_BASE) + (MC_##r)) + (IO_ADDRESS(TEGRA_MC_BASE) + (MC_##r)) #define RA(r) \ - ((u32)IO_ADDRESS(TEGRA_MC_BASE) + (MC_LA_##r)) + (IO_ADDRESS(TEGRA_MC_BASE) + (MC_LA_##r)) #define MASK(x) \ ((0xFFFFFFFFUL >> (31 - (1 ? x) + (0 ? x))) << (0 ? x)) @@ -238,9 +238,9 @@ struct la_scaling_reg_info { }; #define DISP1_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_DISPLAY_BASE) + DS_DISP_MCCIF_##r##_HYST) + (IO_ADDRESS(TEGRA_DISPLAY_BASE) + DS_DISP_MCCIF_##r##_HYST) #define DISP2_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_DISPLAY2_BASE) + DS_DISP_MCCIF_##r##_HYST) + (IO_ADDRESS(TEGRA_DISPLAY2_BASE) + DS_DISP_MCCIF_##r##_HYST) #define DISP_SCALING_REG_INFO(id, r, ra) \ { \ @@ -263,11 +263,11 @@ struct la_scaling_reg_info disp_info[] = { }; #define VI_TH_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_VI_BASE) + VI_MCCIF_##r##_HYST) + (IO_ADDRESS(TEGRA_VI_BASE) + VI_MCCIF_##r##_HYST) #define VI_TM_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_VI_BASE) + VI_TIMEOUT_WOCAL_VI) + (IO_ADDRESS(TEGRA_VI_BASE) + VI_TIMEOUT_WOCAL_VI) #define VI_TL_RA(r) \ - ((u32)IO_ADDRESS(TEGRA_VI_BASE) + VI_RESERVE_##r) + (IO_ADDRESS(TEGRA_VI_BASE) + VI_RESERVE_##r) struct la_scaling_reg_info vi_info[] = { { |