[ARM/tegra] AES: Fix warning triggered by NvRmPhysicalMemUnmap.

The size was incorrect for the DmaVirtAddr, and SrcVirtAddr and
DestVirtAddr were incremented inside the loop, hence were not
the original ones that got mapped.

Also fix two ASSERTs.

Bug 698416

Change-Id: Ia53618f1fe9b3dd45de8194e0d082333c1d9573c
Reviewed-on: http://git-master/r/2833
Reviewed-by: David Le Tacon <dletacon@nvidia.com>
Tested-by: David Le Tacon <dletacon@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

2 files changed, 12 insertions, 7 deletions

diff --git a/arch/arm/mach-tegra/nvddk/nvddk_aes.c b/arch/arm/mach-tegra/nvddk/nvddk_aes.c
index c3f83ca9dfee..2fa264e8af54 100644
--- a/arch/arm/mach-tegra/nvddk/nvddk_aes.c
+++ b/arch/arm/mach-tegra/nvddk/nvddk_aes.c
@@ -1736,20 +1736,21 @@ NvError AesCoreInitEngine(const NvRmDeviceHandle hRmDevice)
         // The slots already dedicated don't depend on which engine is being used but
         // on the capabilities the engines can provide. Basic assumption: both engines have
         // same capabilities.
-        NVDDK_AES_CHECK_INTERFACE_FUNC(pAesHwCtxt, 0, AesGetUsedSlots);
+        NVDDK_AES_CHECK_INTERFACE_FUNC(pAesHwCtxt, 0, AesHwGetUsedSlots);
         pAesHwCtxt->ppEngineCaps[0]->pAesInterf->AesHwGetUsedSlots(gs_pAesCoreEngine);
     }
 
     for (Engine = AesHwEngine_A; Engine < AesHwEngine_Num; Engine++)
     {
         NVDDK_AES_CHECK_INTERFACE(pAesHwCtxt, Engine);
-        NVDDK_AES_CHECK_INTERFACE_FUNC(pAesHwCtxt, Engine, GetIvReadPermissions);
+        NVDDK_AES_CHECK_INTERFACE_FUNC(pAesHwCtxt, Engine, AesHwDisableAllKeyRead);
         pAesHwCtxt->ppEngineCaps[Engine]->pAesInterf->AesHwDisableAllKeyRead(
             pAesHwCtxt,
             Engine,
             pAesHwCtxt->ppEngineCaps[Engine]->NumSlotsSupported);
 
         // Get the Iv read permissions
+        NVDDK_AES_CHECK_INTERFACE_FUNC(pAesHwCtxt, Engine, AesHwGetIvReadPermissions);
         pAesHwCtxt->ppEngineCaps[Engine]->pAesInterf->AesHwGetIvReadPermissions(Engine, pAesHwCtxt);
     }
 
diff --git a/arch/arm/mach-tegra/nvddk/nvddk_aes_core_ap20.c b/arch/arm/mach-tegra/nvddk/nvddk_aes_core_ap20.c
index 1766910013e5..d3296f9dcdc2 100644
--- a/arch/arm/mach-tegra/nvddk/nvddk_aes_core_ap20.c
+++ b/arch/arm/mach-tegra/nvddk/nvddk_aes_core_ap20.c
@@ -510,6 +510,8 @@ NvAesCoreAp20ProcessBuffer(
     NvU32 BytesToProcess = 0;
     NvU32 *pSrcVirAddr = NULL;
     NvU32 *pDestVirAddr = NULL;
+    NvU32 *pSrcVirAddrTmp = NULL;
+    NvU32 *pDestVirAddrTmp = NULL;
     NvU32 *pDmaVirAddr = NULL;
     NvU32 NumBlocks = 0;
     NvError e = NvRmPhysicalMemMap(
@@ -540,6 +542,8 @@ NvAesCoreAp20ProcessBuffer(
         NvOsMemAttribute_Uncached,
         (void **)&pDmaVirAddr));
 
+    pSrcVirAddrTmp = pSrcVirAddr;
+    pDestVirAddrTmp = pDestVirAddr;
     while (TotalBytes)
     {
         if (TotalBytes > AES_HW_DMA_BUFFER_SIZE_BYTES)
@@ -548,23 +552,23 @@ NvAesCoreAp20ProcessBuffer(
             BytesToProcess = TotalBytes;
 
         // Copy data to the DMA buffer from the client buffer
-        NvOsMemcpy((void *)pDmaVirAddr, (void *)pSrcVirAddr, BytesToProcess);
+        NvOsMemcpy((void *)pDmaVirAddr, (void *)pSrcVirAddrTmp, BytesToProcess);
 
         NumBlocks = BytesToProcess / NvDdkAesConst_BlockLengthBytes;
 
         AesHwPrivProcessBuffer(Engine, pEngineVirAddr, DmaPhyAddr, DmaPhyAddr, NumBlocks, IsEncryption, OpMode);
 
         // Copy data from the DMA buffer to the client buffer
-        NvOsMemcpy((void *)pDestVirAddr, (void *)pDmaVirAddr, BytesToProcess);
+        NvOsMemcpy((void *)pDestVirAddrTmp, (void *)pDmaVirAddr, BytesToProcess);
 
         // Increment the buffer pointer
-        pSrcVirAddr += BytesToProcess;
-        pDestVirAddr += BytesToProcess;
+        pSrcVirAddrTmp += BytesToProcess;
+        pDestVirAddrTmp += BytesToProcess;
         TotalBytes -= BytesToProcess;
     }
 
     // UnMap the virtual address
-    NvRmPhysicalMemUnmap(pDmaVirAddr, DataSize);
+    NvRmPhysicalMemUnmap(pDmaVirAddr, AES_HW_DMA_BUFFER_SIZE_BYTES);
 
 fail:
     NvRmPhysicalMemUnmap(pDestVirAddr, DataSize);