[ARM/tegra] add user-level access to NvRm

Change-Id: I901f5a4af15ae8170d3592c42e710535b1cda915

22 files changed, 10201 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/nvrm/Makefile b/arch/arm/mach-tegra/nvrm/Makefile
index ee4c2ad6a43f..0aab604c54af 100644
--- a/arch/arm/mach-tegra/nvrm/Makefile
+++ b/arch/arm/mach-tegra/nvrm/Makefile
@@ -15,3 +15,4 @@ obj-y += io/common/
 obj-y += io/ap15/
 obj-y += io/ap20/
 
+obj-y += dispatch/
\ No newline at end of file
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/Makefile b/arch/arm/mach-tegra/nvrm/dispatch/Makefile
new file mode 100644
index 000000000000..3d65e61d9a47
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/Makefile
@@ -0,0 +1,29 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-y += NvRm_Dispatch.o
+obj-y += nvrm_analog_dispatch.o
+obj-y += nvrm_diag_dispatch.o
+obj-y += nvrm_dma_dispatch.o
+obj-y += nvrm_gpio_dispatch.o
+obj-y += nvrm_i2c_dispatch.o
+obj-y += nvrm_owr_dispatch.o
+obj-y += nvrm_pwm_dispatch.o
+obj-y += nvrm_init_dispatch.o
+obj-y += nvrm_interrupt_dispatch.o
+obj-y += nvrm_memmgr_dispatch.o
+obj-y += nvrm_module_dispatch.o
+obj-y += nvrm_pinmux_dispatch.o
+obj-y += nvrm_power_dispatch.o
+obj-y += nvrm_spi_dispatch.o
+obj-y += nvrm_pmu_dispatch.o
+obj-y += nvrm_keylist_dispatch.o
+obj-y += nvrm_memctrl_dispatch.o
+obj-y += nvrm_transport_dispatch.o
+obj-y += nvrm_xpc_dispatch.o
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/NvRm_Dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/NvRm_Dispatch.c
new file mode 100644
index 000000000000..c0f07cf9f5ed
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/NvRm_Dispatch.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvidlcmd.h"
+#include "nvreftrack.h"
+#include "nvrm_xpc.h"
+#include "nvrm_transport.h"
+#include "nvrm_memctrl.h"
+#include "nvrm_pwm.h"
+#include "nvrm_keylist.h"
+#include "nvrm_pmu.h"
+#include "nvrm_diag.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_analog.h"
+#include "nvrm_owr.h"
+#include "nvrm_i2c.h"
+#include "nvrm_spi.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_dma.h"
+#include "nvrm_power.h"
+#include "nvrm_gpio.h"
+#include "nvrm_module.h"
+#include "nvrm_memmgr.h"
+#include "nvrm_init.h"
+NvError nvrm_xpc_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_transport_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_memctrl_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pwm_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_keylist_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pmu_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_diag_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pinmux_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_analog_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_owr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_i2c_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_spi_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_interrupt_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_dma_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_power_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_gpio_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_module_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_memmgr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_init_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+
+NvError nvrm_pcie_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    return NvError_AccessDenied;
+}
+
+// NvRm Package
+typedef enum
+{
+    NvRm_Invalid = 0,
+    NvRm_nvrm_xpc,
+    NvRm_nvrm_transport,
+    NvRm_nvrm_memctrl,
+    NvRm_nvrm_pcie,
+    NvRm_nvrm_pwm,
+    NvRm_nvrm_keylist,
+    NvRm_nvrm_pmu,
+    NvRm_nvrm_diag,
+    NvRm_nvrm_pinmux,
+    NvRm_nvrm_analog,
+    NvRm_nvrm_owr,
+    NvRm_nvrm_i2c,
+    NvRm_nvrm_spi,
+    NvRm_nvrm_interrupt,
+    NvRm_nvrm_dma,
+    NvRm_nvrm_power,
+    NvRm_nvrm_gpio,
+    NvRm_nvrm_module,
+    NvRm_nvrm_memmgr,
+    NvRm_nvrm_init,
+    NvRm_Num,
+    NvRm_Force32 = 0x7FFFFFFF,
+} NvRm;
+
+typedef NvError (* NvIdlDispatchFunc)( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+
+typedef struct NvIdlDispatchTableRec
+{
+    NvU32 PackageId;
+    NvIdlDispatchFunc DispFunc;
+} NvIdlDispatchTable;
+
+static NvIdlDispatchTable gs_DispatchTable[] =
+{
+    { NvRm_nvrm_xpc, nvrm_xpc_Dispatch },
+    { NvRm_nvrm_transport, nvrm_transport_Dispatch },
+    { NvRm_nvrm_memctrl, nvrm_memctrl_Dispatch },
+    { NvRm_nvrm_pcie, nvrm_pcie_Dispatch },
+    { NvRm_nvrm_pwm, nvrm_pwm_Dispatch },
+    { NvRm_nvrm_keylist, nvrm_keylist_Dispatch },
+    { NvRm_nvrm_pmu, nvrm_pmu_Dispatch },
+    { NvRm_nvrm_diag, nvrm_diag_Dispatch },
+    { NvRm_nvrm_pinmux, nvrm_pinmux_Dispatch },
+    { NvRm_nvrm_analog, nvrm_analog_Dispatch },
+    { NvRm_nvrm_owr, nvrm_owr_Dispatch },
+    { NvRm_nvrm_i2c, nvrm_i2c_Dispatch },
+    { NvRm_nvrm_spi, nvrm_spi_Dispatch },
+    { NvRm_nvrm_interrupt, nvrm_interrupt_Dispatch },
+    { NvRm_nvrm_dma, nvrm_dma_Dispatch },
+    { NvRm_nvrm_power, nvrm_power_Dispatch },
+    { NvRm_nvrm_gpio, nvrm_gpio_Dispatch },
+    { NvRm_nvrm_module, nvrm_module_Dispatch },
+    { NvRm_nvrm_memmgr, nvrm_memmgr_Dispatch },
+    { NvRm_nvrm_init, nvrm_init_Dispatch },
+    { 0 },
+};
+
+NvError NvRm_Dispatch( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvU32 packid_;
+    NvU32 funcid_;
+    NvIdlDispatchTable *table_;
+
+    NV_ASSERT( InBuffer );
+    NV_ASSERT( OutBuffer );
+
+    packid_ = ((NvU32 *)InBuffer)[0];
+    funcid_ = ((NvU32 *)InBuffer)[1];
+    table_ = gs_DispatchTable;
+
+    if ( packid_-1 >= NV_ARRAY_SIZE(gs_DispatchTable) ||
+         !table_[packid_ - 1].DispFunc )
+        return NvError_IoctlFailed;
+
+    return table_[packid_ - 1].DispFunc( funcid_, InBuffer, InSize,
+        OutBuffer, OutSize, Ctx );
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_analog_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_analog_dispatch.c
new file mode 100644
index 000000000000..a94b79914907
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_analog_dispatch.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_analog.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmUsbDetectChargerState_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 wait;
+} NV_ALIGN(4) NvRmUsbDetectChargerState_in;
+
+typedef struct NvRmUsbDetectChargerState_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmUsbDetectChargerState_inout;
+
+typedef struct NvRmUsbDetectChargerState_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmUsbDetectChargerState_out;
+
+typedef struct NvRmUsbDetectChargerState_params_t
+{
+    NvRmUsbDetectChargerState_in in;
+    NvRmUsbDetectChargerState_inout inout;
+    NvRmUsbDetectChargerState_out out;
+} NvRmUsbDetectChargerState_params;
+
+typedef struct NvRmUsbIsConnected_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmUsbIsConnected_in;
+
+typedef struct NvRmUsbIsConnected_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmUsbIsConnected_inout;
+
+typedef struct NvRmUsbIsConnected_out_t
+{
+    NvBool ret_;
+} NV_ALIGN(4) NvRmUsbIsConnected_out;
+
+typedef struct NvRmUsbIsConnected_params_t
+{
+    NvRmUsbIsConnected_in in;
+    NvRmUsbIsConnected_inout inout;
+    NvRmUsbIsConnected_out out;
+} NvRmUsbIsConnected_params;
+
+typedef struct NvRmAnalogGetTvDacConfiguration_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmAnalogTvDacType Type;
+} NV_ALIGN(4) NvRmAnalogGetTvDacConfiguration_in;
+
+typedef struct NvRmAnalogGetTvDacConfiguration_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmAnalogGetTvDacConfiguration_inout;
+
+typedef struct NvRmAnalogGetTvDacConfiguration_out_t
+{
+    NvU8 ret_;
+} NV_ALIGN(4) NvRmAnalogGetTvDacConfiguration_out;
+
+typedef struct NvRmAnalogGetTvDacConfiguration_params_t
+{
+    NvRmAnalogGetTvDacConfiguration_in in;
+    NvRmAnalogGetTvDacConfiguration_inout inout;
+    NvRmAnalogGetTvDacConfiguration_out out;
+} NvRmAnalogGetTvDacConfiguration_params;
+
+typedef struct NvRmAnalogInterfaceControl_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmAnalogInterface Interface;
+    NvBool Enable;
+    void* Config;
+    NvU32 ConfigLength;
+} NV_ALIGN(4) NvRmAnalogInterfaceControl_in;
+
+typedef struct NvRmAnalogInterfaceControl_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmAnalogInterfaceControl_inout;
+
+typedef struct NvRmAnalogInterfaceControl_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmAnalogInterfaceControl_out;
+
+typedef struct NvRmAnalogInterfaceControl_params_t
+{
+    NvRmAnalogInterfaceControl_in in;
+    NvRmAnalogInterfaceControl_inout inout;
+    NvRmAnalogInterfaceControl_out out;
+} NvRmAnalogInterfaceControl_params;
+
+static NvError NvRmUsbDetectChargerState_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmUsbDetectChargerState_in *p_in;
+    NvRmUsbDetectChargerState_out *p_out;
+
+    p_in = (NvRmUsbDetectChargerState_in *)InBuffer;
+    p_out = (NvRmUsbDetectChargerState_out *)((NvU8 *)OutBuffer + OFFSET(NvRmUsbDetectChargerState_params, out) - OFFSET(NvRmUsbDetectChargerState_params, inout));
+
+
+    p_out->ret_ = NvRmUsbDetectChargerState( p_in->hDevice, p_in->wait );
+
+    return err_;
+}
+
+static NvError NvRmUsbIsConnected_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmUsbIsConnected_in *p_in;
+    NvRmUsbIsConnected_out *p_out;
+
+    p_in = (NvRmUsbIsConnected_in *)InBuffer;
+    p_out = (NvRmUsbIsConnected_out *)((NvU8 *)OutBuffer + OFFSET(NvRmUsbIsConnected_params, out) - OFFSET(NvRmUsbIsConnected_params, inout));
+
+
+    p_out->ret_ = NvRmUsbIsConnected( p_in->hDevice );
+
+    return err_;
+}
+
+static NvError NvRmAnalogGetTvDacConfiguration_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmAnalogGetTvDacConfiguration_in *p_in;
+    NvRmAnalogGetTvDacConfiguration_out *p_out;
+
+    p_in = (NvRmAnalogGetTvDacConfiguration_in *)InBuffer;
+    p_out = (NvRmAnalogGetTvDacConfiguration_out *)((NvU8 *)OutBuffer + OFFSET(NvRmAnalogGetTvDacConfiguration_params, out) - OFFSET(NvRmAnalogGetTvDacConfiguration_params, inout));
+
+
+    p_out->ret_ = NvRmAnalogGetTvDacConfiguration( p_in->hDevice, p_in->Type );
+
+    return err_;
+}
+
+static NvError NvRmAnalogInterfaceControl_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmAnalogInterfaceControl_in *p_in;
+    NvRmAnalogInterfaceControl_out *p_out;
+    void*  Config = NULL;
+
+    p_in = (NvRmAnalogInterfaceControl_in *)InBuffer;
+    p_out = (NvRmAnalogInterfaceControl_out *)((NvU8 *)OutBuffer + OFFSET(NvRmAnalogInterfaceControl_params, out) - OFFSET(NvRmAnalogInterfaceControl_params, inout));
+
+    if( p_in->ConfigLength && p_in->Config )
+    {
+        Config = (void*  )NvOsAlloc( p_in->ConfigLength );
+        if( !Config )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Config )
+        {
+            err_ = NvOsCopyIn( Config, p_in->Config, p_in->ConfigLength );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmAnalogInterfaceControl( p_in->hDevice, p_in->Interface, p_in->Enable, Config, p_in->ConfigLength );
+
+    if(p_in->Config && Config)
+    {
+        err_ = NvOsCopyOut( p_in->Config, Config, p_in->ConfigLength );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( Config );
+    return err_;
+}
+
+NvError nvrm_analog_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_analog_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 3:
+        err_ = NvRmUsbDetectChargerState_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmUsbIsConnected_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmAnalogGetTvDacConfiguration_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmAnalogInterfaceControl_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_diag_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_diag_dispatch.c
new file mode 100644
index 000000000000..b521ca38d815
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_diag_dispatch.c
@@ -0,0 +1,1078 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_diag.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmDiagGetTemperature_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmTmonZoneId ZoneId;
+} NV_ALIGN(4) NvRmDiagGetTemperature_in;
+
+typedef struct NvRmDiagGetTemperature_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagGetTemperature_inout;
+
+typedef struct NvRmDiagGetTemperature_out_t
+{
+    NvError ret_;
+    NvS32 pTemperatureC;
+} NV_ALIGN(4) NvRmDiagGetTemperature_out;
+
+typedef struct NvRmDiagGetTemperature_params_t
+{
+    NvRmDiagGetTemperature_in in;
+    NvRmDiagGetTemperature_inout inout;
+    NvRmDiagGetTemperature_out out;
+} NvRmDiagGetTemperature_params;
+
+typedef struct NvRmDiagIsLockSupported_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+} NV_ALIGN(4) NvRmDiagIsLockSupported_in;
+
+typedef struct NvRmDiagIsLockSupported_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagIsLockSupported_inout;
+
+typedef struct NvRmDiagIsLockSupported_out_t
+{
+    NvBool ret_;
+} NV_ALIGN(4) NvRmDiagIsLockSupported_out;
+
+typedef struct NvRmDiagIsLockSupported_params_t
+{
+    NvRmDiagIsLockSupported_in in;
+    NvRmDiagIsLockSupported_inout inout;
+    NvRmDiagIsLockSupported_out out;
+} NvRmDiagIsLockSupported_params;
+
+typedef struct NvRmDiagConfigurePowerRail_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagPowerRailHandle hRail;
+    NvU32 VoltageMV;
+} NV_ALIGN(4) NvRmDiagConfigurePowerRail_in;
+
+typedef struct NvRmDiagConfigurePowerRail_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagConfigurePowerRail_inout;
+
+typedef struct NvRmDiagConfigurePowerRail_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagConfigurePowerRail_out;
+
+typedef struct NvRmDiagConfigurePowerRail_params_t
+{
+    NvRmDiagConfigurePowerRail_in in;
+    NvRmDiagConfigurePowerRail_inout inout;
+    NvRmDiagConfigurePowerRail_out out;
+} NvRmDiagConfigurePowerRail_params;
+
+typedef struct NvRmDiagModuleListPowerRails_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID id;
+    NvRmDiagPowerRailHandle  * phRailList;
+} NV_ALIGN(4) NvRmDiagModuleListPowerRails_in;
+
+typedef struct NvRmDiagModuleListPowerRails_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagModuleListPowerRails_inout;
+
+typedef struct NvRmDiagModuleListPowerRails_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagModuleListPowerRails_out;
+
+typedef struct NvRmDiagModuleListPowerRails_params_t
+{
+    NvRmDiagModuleListPowerRails_in in;
+    NvRmDiagModuleListPowerRails_inout inout;
+    NvRmDiagModuleListPowerRails_out out;
+} NvRmDiagModuleListPowerRails_params;
+
+typedef struct NvRmDiagPowerRailGetName_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagPowerRailHandle hRail;
+} NV_ALIGN(4) NvRmDiagPowerRailGetName_in;
+
+typedef struct NvRmDiagPowerRailGetName_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagPowerRailGetName_inout;
+
+typedef struct NvRmDiagPowerRailGetName_out_t
+{
+    NvU64 ret_;
+} NV_ALIGN(4) NvRmDiagPowerRailGetName_out;
+
+typedef struct NvRmDiagPowerRailGetName_params_t
+{
+    NvRmDiagPowerRailGetName_in in;
+    NvRmDiagPowerRailGetName_inout inout;
+    NvRmDiagPowerRailGetName_out out;
+} NvRmDiagPowerRailGetName_params;
+
+typedef struct NvRmDiagListPowerRails_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagPowerRailHandle  * phRailList;
+} NV_ALIGN(4) NvRmDiagListPowerRails_in;
+
+typedef struct NvRmDiagListPowerRails_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagListPowerRails_inout;
+
+typedef struct NvRmDiagListPowerRails_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagListPowerRails_out;
+
+typedef struct NvRmDiagListPowerRails_params_t
+{
+    NvRmDiagListPowerRails_in in;
+    NvRmDiagListPowerRails_inout inout;
+    NvRmDiagListPowerRails_out out;
+} NvRmDiagListPowerRails_params;
+
+typedef struct NvRmDiagModuleReset_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID id;
+    NvBool KeepAsserted;
+} NV_ALIGN(4) NvRmDiagModuleReset_in;
+
+typedef struct NvRmDiagModuleReset_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagModuleReset_inout;
+
+typedef struct NvRmDiagModuleReset_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagModuleReset_out;
+
+typedef struct NvRmDiagModuleReset_params_t
+{
+    NvRmDiagModuleReset_in in;
+    NvRmDiagModuleReset_inout inout;
+    NvRmDiagModuleReset_out out;
+} NvRmDiagModuleReset_params;
+
+typedef struct NvRmDiagClockScalerConfigure_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hScaler;
+    NvRmDiagClockSourceHandle hInput;
+    NvU32 M;
+    NvU32 N;
+} NV_ALIGN(4) NvRmDiagClockScalerConfigure_in;
+
+typedef struct NvRmDiagClockScalerConfigure_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagClockScalerConfigure_inout;
+
+typedef struct NvRmDiagClockScalerConfigure_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagClockScalerConfigure_out;
+
+typedef struct NvRmDiagClockScalerConfigure_params_t
+{
+    NvRmDiagClockScalerConfigure_in in;
+    NvRmDiagClockScalerConfigure_inout inout;
+    NvRmDiagClockScalerConfigure_out out;
+} NvRmDiagClockScalerConfigure_params;
+
+typedef struct NvRmDiagPllConfigure_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hPll;
+    NvU32 M;
+    NvU32 N;
+    NvU32 P;
+} NV_ALIGN(4) NvRmDiagPllConfigure_in;
+
+typedef struct NvRmDiagPllConfigure_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagPllConfigure_inout;
+
+typedef struct NvRmDiagPllConfigure_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagPllConfigure_out;
+
+typedef struct NvRmDiagPllConfigure_params_t
+{
+    NvRmDiagPllConfigure_in in;
+    NvRmDiagPllConfigure_inout inout;
+    NvRmDiagPllConfigure_out out;
+} NvRmDiagPllConfigure_params;
+
+typedef struct NvRmDiagOscillatorGetFreq_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hOscillator;
+} NV_ALIGN(4) NvRmDiagOscillatorGetFreq_in;
+
+typedef struct NvRmDiagOscillatorGetFreq_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagOscillatorGetFreq_inout;
+
+typedef struct NvRmDiagOscillatorGetFreq_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmDiagOscillatorGetFreq_out;
+
+typedef struct NvRmDiagOscillatorGetFreq_params_t
+{
+    NvRmDiagOscillatorGetFreq_in in;
+    NvRmDiagOscillatorGetFreq_inout inout;
+    NvRmDiagOscillatorGetFreq_out out;
+} NvRmDiagOscillatorGetFreq_params;
+
+typedef struct NvRmDiagClockSourceListSources_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hSource;
+    NvRmDiagClockSourceHandle  * phSourceList;
+} NV_ALIGN(4) NvRmDiagClockSourceListSources_in;
+
+typedef struct NvRmDiagClockSourceListSources_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagClockSourceListSources_inout;
+
+typedef struct NvRmDiagClockSourceListSources_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagClockSourceListSources_out;
+
+typedef struct NvRmDiagClockSourceListSources_params_t
+{
+    NvRmDiagClockSourceListSources_in in;
+    NvRmDiagClockSourceListSources_inout inout;
+    NvRmDiagClockSourceListSources_out out;
+} NvRmDiagClockSourceListSources_params;
+
+typedef struct NvRmDiagClockSourceGetScaler_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hSource;
+} NV_ALIGN(4) NvRmDiagClockSourceGetScaler_in;
+
+typedef struct NvRmDiagClockSourceGetScaler_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetScaler_inout;
+
+typedef struct NvRmDiagClockSourceGetScaler_out_t
+{
+    NvRmDiagClockScalerType ret_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetScaler_out;
+
+typedef struct NvRmDiagClockSourceGetScaler_params_t
+{
+    NvRmDiagClockSourceGetScaler_in in;
+    NvRmDiagClockSourceGetScaler_inout inout;
+    NvRmDiagClockSourceGetScaler_out out;
+} NvRmDiagClockSourceGetScaler_params;
+
+typedef struct NvRmDiagClockSourceGetType_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hSource;
+} NV_ALIGN(4) NvRmDiagClockSourceGetType_in;
+
+typedef struct NvRmDiagClockSourceGetType_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetType_inout;
+
+typedef struct NvRmDiagClockSourceGetType_out_t
+{
+    NvRmDiagClockSourceType ret_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetType_out;
+
+typedef struct NvRmDiagClockSourceGetType_params_t
+{
+    NvRmDiagClockSourceGetType_in in;
+    NvRmDiagClockSourceGetType_inout inout;
+    NvRmDiagClockSourceGetType_out out;
+} NvRmDiagClockSourceGetType_params;
+
+typedef struct NvRmDiagClockSourceGetName_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hSource;
+} NV_ALIGN(4) NvRmDiagClockSourceGetName_in;
+
+typedef struct NvRmDiagClockSourceGetName_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetName_inout;
+
+typedef struct NvRmDiagClockSourceGetName_out_t
+{
+    NvU64 ret_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetName_out;
+
+typedef struct NvRmDiagClockSourceGetName_params_t
+{
+    NvRmDiagClockSourceGetName_in in;
+    NvRmDiagClockSourceGetName_inout inout;
+    NvRmDiagClockSourceGetName_out out;
+} NvRmDiagClockSourceGetName_params;
+
+typedef struct NvRmDiagModuleClockConfigure_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID id;
+    NvRmDiagClockSourceHandle hSource;
+    NvU32 divider;
+    NvBool Source1st;
+} NV_ALIGN(4) NvRmDiagModuleClockConfigure_in;
+
+typedef struct NvRmDiagModuleClockConfigure_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagModuleClockConfigure_inout;
+
+typedef struct NvRmDiagModuleClockConfigure_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagModuleClockConfigure_out;
+
+typedef struct NvRmDiagModuleClockConfigure_params_t
+{
+    NvRmDiagModuleClockConfigure_in in;
+    NvRmDiagModuleClockConfigure_inout inout;
+    NvRmDiagModuleClockConfigure_out out;
+} NvRmDiagModuleClockConfigure_params;
+
+typedef struct NvRmDiagModuleClockEnable_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID id;
+    NvBool enable;
+} NV_ALIGN(4) NvRmDiagModuleClockEnable_in;
+
+typedef struct NvRmDiagModuleClockEnable_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagModuleClockEnable_inout;
+
+typedef struct NvRmDiagModuleClockEnable_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagModuleClockEnable_out;
+
+typedef struct NvRmDiagModuleClockEnable_params_t
+{
+    NvRmDiagModuleClockEnable_in in;
+    NvRmDiagModuleClockEnable_inout inout;
+    NvRmDiagModuleClockEnable_out out;
+} NvRmDiagModuleClockEnable_params;
+
+typedef struct NvRmDiagModuleListClockSources_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID id;
+    NvRmDiagClockSourceHandle  * phSourceList;
+} NV_ALIGN(4) NvRmDiagModuleListClockSources_in;
+
+typedef struct NvRmDiagModuleListClockSources_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagModuleListClockSources_inout;
+
+typedef struct NvRmDiagModuleListClockSources_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagModuleListClockSources_out;
+
+typedef struct NvRmDiagModuleListClockSources_params_t
+{
+    NvRmDiagModuleListClockSources_in in;
+    NvRmDiagModuleListClockSources_inout inout;
+    NvRmDiagModuleListClockSources_out out;
+} NvRmDiagModuleListClockSources_params;
+
+typedef struct NvRmDiagListClockSources_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle  * phSourceList;
+} NV_ALIGN(4) NvRmDiagListClockSources_in;
+
+typedef struct NvRmDiagListClockSources_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagListClockSources_inout;
+
+typedef struct NvRmDiagListClockSources_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagListClockSources_out;
+
+typedef struct NvRmDiagListClockSources_params_t
+{
+    NvRmDiagListClockSources_in in;
+    NvRmDiagListClockSources_inout inout;
+    NvRmDiagListClockSources_out out;
+} NvRmDiagListClockSources_params;
+
+typedef struct NvRmDiagListModules_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID  * pIdList;
+} NV_ALIGN(4) NvRmDiagListModules_in;
+
+typedef struct NvRmDiagListModules_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagListModules_inout;
+
+typedef struct NvRmDiagListModules_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagListModules_out;
+
+typedef struct NvRmDiagListModules_params_t
+{
+    NvRmDiagListModules_in in;
+    NvRmDiagListModules_inout inout;
+    NvRmDiagListModules_out out;
+} NvRmDiagListModules_params;
+
+typedef struct NvRmDiagEnable_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmDiagEnable_in;
+
+typedef struct NvRmDiagEnable_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagEnable_inout;
+
+typedef struct NvRmDiagEnable_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagEnable_out;
+
+typedef struct NvRmDiagEnable_params_t
+{
+    NvRmDiagEnable_in in;
+    NvRmDiagEnable_inout inout;
+    NvRmDiagEnable_out out;
+} NvRmDiagEnable_params;
+
+static NvError NvRmDiagGetTemperature_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagGetTemperature_in *p_in;
+    NvRmDiagGetTemperature_out *p_out;
+
+    p_in = (NvRmDiagGetTemperature_in *)InBuffer;
+    p_out = (NvRmDiagGetTemperature_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagGetTemperature_params, out) - OFFSET(NvRmDiagGetTemperature_params, inout));
+
+
+    p_out->ret_ = NvRmDiagGetTemperature( p_in->hRmDeviceHandle, p_in->ZoneId, &p_out->pTemperatureC );
+
+    return err_;
+}
+
+static NvError NvRmDiagIsLockSupported_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagIsLockSupported_out *p_out;
+    p_out = (NvRmDiagIsLockSupported_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagIsLockSupported_params, out) - OFFSET(NvRmDiagIsLockSupported_params, inout));
+
+
+    p_out->ret_ = NvRmDiagIsLockSupported(  );
+
+    return err_;
+}
+
+static NvError NvRmDiagConfigurePowerRail_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagConfigurePowerRail_in *p_in;
+    NvRmDiagConfigurePowerRail_out *p_out;
+
+    p_in = (NvRmDiagConfigurePowerRail_in *)InBuffer;
+    p_out = (NvRmDiagConfigurePowerRail_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagConfigurePowerRail_params, out) - OFFSET(NvRmDiagConfigurePowerRail_params, inout));
+
+
+    p_out->ret_ = NvRmDiagConfigurePowerRail( p_in->hRail, p_in->VoltageMV );
+
+    return err_;
+}
+
+static NvError NvRmDiagModuleListPowerRails_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagModuleListPowerRails_in *p_in;
+    NvRmDiagModuleListPowerRails_inout *p_inout;
+    NvRmDiagModuleListPowerRails_out *p_out;
+    NvRmDiagModuleListPowerRails_inout inout;
+    NvRmDiagPowerRailHandle *phRailList = NULL;
+
+    p_in = (NvRmDiagModuleListPowerRails_in *)InBuffer;
+    p_inout = (NvRmDiagModuleListPowerRails_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagModuleListPowerRails_params, inout));
+    p_out = (NvRmDiagModuleListPowerRails_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagModuleListPowerRails_params, out) - OFFSET(NvRmDiagModuleListPowerRails_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->phRailList )
+    {
+        phRailList = (NvRmDiagPowerRailHandle  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagPowerRailHandle  ) );
+        if( !phRailList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagModuleListPowerRails( p_in->id, &inout.pListSize, phRailList );
+
+
+    p_inout = (NvRmDiagModuleListPowerRails_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->phRailList && phRailList)
+    {
+        err_ = NvOsCopyOut( p_in->phRailList, phRailList, p_inout->pListSize * sizeof( NvRmDiagPowerRailHandle  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( phRailList );
+    return err_;
+}
+
+static NvError NvRmDiagPowerRailGetName_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagPowerRailGetName_in *p_in;
+    NvRmDiagPowerRailGetName_out *p_out;
+
+    p_in = (NvRmDiagPowerRailGetName_in *)InBuffer;
+    p_out = (NvRmDiagPowerRailGetName_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagPowerRailGetName_params, out) - OFFSET(NvRmDiagPowerRailGetName_params, inout));
+
+
+    p_out->ret_ = NvRmDiagPowerRailGetName( p_in->hRail );
+
+    return err_;
+}
+
+static NvError NvRmDiagListPowerRails_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagListPowerRails_in *p_in;
+    NvRmDiagListPowerRails_inout *p_inout;
+    NvRmDiagListPowerRails_out *p_out;
+    NvRmDiagListPowerRails_inout inout;
+    NvRmDiagPowerRailHandle *phRailList = NULL;
+
+    p_in = (NvRmDiagListPowerRails_in *)InBuffer;
+    p_inout = (NvRmDiagListPowerRails_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagListPowerRails_params, inout));
+    p_out = (NvRmDiagListPowerRails_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagListPowerRails_params, out) - OFFSET(NvRmDiagListPowerRails_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->phRailList )
+    {
+        phRailList = (NvRmDiagPowerRailHandle  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagPowerRailHandle  ) );
+        if( !phRailList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagListPowerRails( &inout.pListSize, phRailList );
+
+
+    p_inout = (NvRmDiagListPowerRails_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->phRailList && phRailList)
+    {
+        err_ = NvOsCopyOut( p_in->phRailList, phRailList, p_inout->pListSize * sizeof( NvRmDiagPowerRailHandle  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( phRailList );
+    return err_;
+}
+
+static NvError NvRmDiagModuleReset_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagModuleReset_in *p_in;
+    NvRmDiagModuleReset_out *p_out;
+
+    p_in = (NvRmDiagModuleReset_in *)InBuffer;
+    p_out = (NvRmDiagModuleReset_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagModuleReset_params, out) - OFFSET(NvRmDiagModuleReset_params, inout));
+
+
+    p_out->ret_ = NvRmDiagModuleReset( p_in->id, p_in->KeepAsserted );
+
+    return err_;
+}
+
+static NvError NvRmDiagClockScalerConfigure_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagClockScalerConfigure_in *p_in;
+    NvRmDiagClockScalerConfigure_out *p_out;
+
+    p_in = (NvRmDiagClockScalerConfigure_in *)InBuffer;
+    p_out = (NvRmDiagClockScalerConfigure_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagClockScalerConfigure_params, out) - OFFSET(NvRmDiagClockScalerConfigure_params, inout));
+
+
+    p_out->ret_ = NvRmDiagClockScalerConfigure( p_in->hScaler, p_in->hInput, p_in->M, p_in->N );
+
+    return err_;
+}
+
+static NvError NvRmDiagPllConfigure_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagPllConfigure_in *p_in;
+    NvRmDiagPllConfigure_out *p_out;
+
+    p_in = (NvRmDiagPllConfigure_in *)InBuffer;
+    p_out = (NvRmDiagPllConfigure_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagPllConfigure_params, out) - OFFSET(NvRmDiagPllConfigure_params, inout));
+
+
+    p_out->ret_ = NvRmDiagPllConfigure( p_in->hPll, p_in->M, p_in->N, p_in->P );
+
+    return err_;
+}
+
+static NvError NvRmDiagOscillatorGetFreq_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagOscillatorGetFreq_in *p_in;
+    NvRmDiagOscillatorGetFreq_out *p_out;
+
+    p_in = (NvRmDiagOscillatorGetFreq_in *)InBuffer;
+    p_out = (NvRmDiagOscillatorGetFreq_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagOscillatorGetFreq_params, out) - OFFSET(NvRmDiagOscillatorGetFreq_params, inout));
+
+
+    p_out->ret_ = NvRmDiagOscillatorGetFreq( p_in->hOscillator );
+
+    return err_;
+}
+
+static NvError NvRmDiagClockSourceListSources_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagClockSourceListSources_in *p_in;
+    NvRmDiagClockSourceListSources_inout *p_inout;
+    NvRmDiagClockSourceListSources_out *p_out;
+    NvRmDiagClockSourceListSources_inout inout;
+    NvRmDiagClockSourceHandle *phSourceList = NULL;
+
+    p_in = (NvRmDiagClockSourceListSources_in *)InBuffer;
+    p_inout = (NvRmDiagClockSourceListSources_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagClockSourceListSources_params, inout));
+    p_out = (NvRmDiagClockSourceListSources_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagClockSourceListSources_params, out) - OFFSET(NvRmDiagClockSourceListSources_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->phSourceList )
+    {
+        phSourceList = (NvRmDiagClockSourceHandle  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( !phSourceList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagClockSourceListSources( p_in->hSource, &inout.pListSize, phSourceList );
+
+
+    p_inout = (NvRmDiagClockSourceListSources_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->phSourceList && phSourceList)
+    {
+        err_ = NvOsCopyOut( p_in->phSourceList, phSourceList, p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( phSourceList );
+    return err_;
+}
+
+static NvError NvRmDiagClockSourceGetScaler_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagClockSourceGetScaler_in *p_in;
+    NvRmDiagClockSourceGetScaler_out *p_out;
+
+    p_in = (NvRmDiagClockSourceGetScaler_in *)InBuffer;
+    p_out = (NvRmDiagClockSourceGetScaler_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagClockSourceGetScaler_params, out) - OFFSET(NvRmDiagClockSourceGetScaler_params, inout));
+
+
+    p_out->ret_ = NvRmDiagClockSourceGetScaler( p_in->hSource );
+
+    return err_;
+}
+
+static NvError NvRmDiagClockSourceGetType_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagClockSourceGetType_in *p_in;
+    NvRmDiagClockSourceGetType_out *p_out;
+
+    p_in = (NvRmDiagClockSourceGetType_in *)InBuffer;
+    p_out = (NvRmDiagClockSourceGetType_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagClockSourceGetType_params, out) - OFFSET(NvRmDiagClockSourceGetType_params, inout));
+
+
+    p_out->ret_ = NvRmDiagClockSourceGetType( p_in->hSource );
+
+    return err_;
+}
+
+static NvError NvRmDiagClockSourceGetName_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagClockSourceGetName_in *p_in;
+    NvRmDiagClockSourceGetName_out *p_out;
+
+    p_in = (NvRmDiagClockSourceGetName_in *)InBuffer;
+    p_out = (NvRmDiagClockSourceGetName_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagClockSourceGetName_params, out) - OFFSET(NvRmDiagClockSourceGetName_params, inout));
+
+
+    p_out->ret_ = NvRmDiagClockSourceGetName( p_in->hSource );
+
+    return err_;
+}
+
+static NvError NvRmDiagModuleClockConfigure_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagModuleClockConfigure_in *p_in;
+    NvRmDiagModuleClockConfigure_out *p_out;
+
+    p_in = (NvRmDiagModuleClockConfigure_in *)InBuffer;
+    p_out = (NvRmDiagModuleClockConfigure_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagModuleClockConfigure_params, out) - OFFSET(NvRmDiagModuleClockConfigure_params, inout));
+
+
+    p_out->ret_ = NvRmDiagModuleClockConfigure( p_in->id, p_in->hSource, p_in->divider, p_in->Source1st );
+
+    return err_;
+}
+
+static NvError NvRmDiagModuleClockEnable_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagModuleClockEnable_in *p_in;
+    NvRmDiagModuleClockEnable_out *p_out;
+
+    p_in = (NvRmDiagModuleClockEnable_in *)InBuffer;
+    p_out = (NvRmDiagModuleClockEnable_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagModuleClockEnable_params, out) - OFFSET(NvRmDiagModuleClockEnable_params, inout));
+
+
+    p_out->ret_ = NvRmDiagModuleClockEnable( p_in->id, p_in->enable );
+
+    return err_;
+}
+
+static NvError NvRmDiagModuleListClockSources_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagModuleListClockSources_in *p_in;
+    NvRmDiagModuleListClockSources_inout *p_inout;
+    NvRmDiagModuleListClockSources_out *p_out;
+    NvRmDiagModuleListClockSources_inout inout;
+    NvRmDiagClockSourceHandle *phSourceList = NULL;
+
+    p_in = (NvRmDiagModuleListClockSources_in *)InBuffer;
+    p_inout = (NvRmDiagModuleListClockSources_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagModuleListClockSources_params, inout));
+    p_out = (NvRmDiagModuleListClockSources_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagModuleListClockSources_params, out) - OFFSET(NvRmDiagModuleListClockSources_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->phSourceList )
+    {
+        phSourceList = (NvRmDiagClockSourceHandle  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( !phSourceList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagModuleListClockSources( p_in->id, &inout.pListSize, phSourceList );
+
+
+    p_inout = (NvRmDiagModuleListClockSources_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->phSourceList && phSourceList)
+    {
+        err_ = NvOsCopyOut( p_in->phSourceList, phSourceList, p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( phSourceList );
+    return err_;
+}
+
+static NvError NvRmDiagListClockSources_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagListClockSources_in *p_in;
+    NvRmDiagListClockSources_inout *p_inout;
+    NvRmDiagListClockSources_out *p_out;
+    NvRmDiagListClockSources_inout inout;
+    NvRmDiagClockSourceHandle *phSourceList = NULL;
+
+    p_in = (NvRmDiagListClockSources_in *)InBuffer;
+    p_inout = (NvRmDiagListClockSources_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagListClockSources_params, inout));
+    p_out = (NvRmDiagListClockSources_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagListClockSources_params, out) - OFFSET(NvRmDiagListClockSources_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->phSourceList )
+    {
+        phSourceList = (NvRmDiagClockSourceHandle  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( !phSourceList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagListClockSources( &inout.pListSize, phSourceList );
+
+
+    p_inout = (NvRmDiagListClockSources_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->phSourceList && phSourceList)
+    {
+        err_ = NvOsCopyOut( p_in->phSourceList, phSourceList, p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( phSourceList );
+    return err_;
+}
+
+static NvError NvRmDiagListModules_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagListModules_in *p_in;
+    NvRmDiagListModules_inout *p_inout;
+    NvRmDiagListModules_out *p_out;
+    NvRmDiagListModules_inout inout;
+    NvRmDiagModuleID *pIdList = NULL;
+
+    p_in = (NvRmDiagListModules_in *)InBuffer;
+    p_inout = (NvRmDiagListModules_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagListModules_params, inout));
+    p_out = (NvRmDiagListModules_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagListModules_params, out) - OFFSET(NvRmDiagListModules_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->pIdList )
+    {
+        pIdList = (NvRmDiagModuleID  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagModuleID  ) );
+        if( !pIdList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagListModules( &inout.pListSize, pIdList );
+
+
+    p_inout = (NvRmDiagListModules_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->pIdList && pIdList)
+    {
+        err_ = NvOsCopyOut( p_in->pIdList, pIdList, p_inout->pListSize * sizeof( NvRmDiagModuleID  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pIdList );
+    return err_;
+}
+
+static NvError NvRmDiagEnable_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagEnable_in *p_in;
+    NvRmDiagEnable_out *p_out;
+
+    p_in = (NvRmDiagEnable_in *)InBuffer;
+    p_out = (NvRmDiagEnable_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagEnable_params, out) - OFFSET(NvRmDiagEnable_params, inout));
+
+
+    p_out->ret_ = NvRmDiagEnable( p_in->hDevice );
+
+    return err_;
+}
+
+NvError nvrm_diag_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_diag_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 19:
+        err_ = NvRmDiagGetTemperature_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 18:
+        err_ = NvRmDiagIsLockSupported_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 17:
+        err_ = NvRmDiagConfigurePowerRail_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 16:
+        err_ = NvRmDiagModuleListPowerRails_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 15:
+        err_ = NvRmDiagPowerRailGetName_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 14:
+        err_ = NvRmDiagListPowerRails_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 13:
+        err_ = NvRmDiagModuleReset_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 12:
+        err_ = NvRmDiagClockScalerConfigure_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 11:
+        err_ = NvRmDiagPllConfigure_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 10:
+        err_ = NvRmDiagOscillatorGetFreq_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 9:
+        err_ = NvRmDiagClockSourceListSources_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRmDiagClockSourceGetScaler_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmDiagClockSourceGetType_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmDiagClockSourceGetName_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmDiagModuleClockConfigure_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmDiagModuleClockEnable_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmDiagModuleListClockSources_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmDiagListClockSources_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmDiagListModules_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmDiagEnable_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_dma_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_dma_dispatch.c
new file mode 100644
index 000000000000..ff246393b5ef
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_dma_dispatch.c
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_dma.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmDmaIsDmaTransferCompletes_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDmaHandle hDma;
+    NvBool IsFirstHalfBuffer;
+} NV_ALIGN(4) NvRmDmaIsDmaTransferCompletes_in;
+
+typedef struct NvRmDmaIsDmaTransferCompletes_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaIsDmaTransferCompletes_inout;
+
+typedef struct NvRmDmaIsDmaTransferCompletes_out_t
+{
+    NvBool ret_;
+} NV_ALIGN(4) NvRmDmaIsDmaTransferCompletes_out;
+
+typedef struct NvRmDmaIsDmaTransferCompletes_params_t
+{
+    NvRmDmaIsDmaTransferCompletes_in in;
+    NvRmDmaIsDmaTransferCompletes_inout inout;
+    NvRmDmaIsDmaTransferCompletes_out out;
+} NvRmDmaIsDmaTransferCompletes_params;
+
+typedef struct NvRmDmaGetTransferredCount_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDmaHandle hDma;
+    NvBool IsTransferStop;
+} NV_ALIGN(4) NvRmDmaGetTransferredCount_in;
+
+typedef struct NvRmDmaGetTransferredCount_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaGetTransferredCount_inout;
+
+typedef struct NvRmDmaGetTransferredCount_out_t
+{
+    NvError ret_;
+    NvU32 pTransferCount;
+} NV_ALIGN(4) NvRmDmaGetTransferredCount_out;
+
+typedef struct NvRmDmaGetTransferredCount_params_t
+{
+    NvRmDmaGetTransferredCount_in in;
+    NvRmDmaGetTransferredCount_inout inout;
+    NvRmDmaGetTransferredCount_out out;
+} NvRmDmaGetTransferredCount_params;
+
+typedef struct NvRmDmaAbort_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDmaHandle hDma;
+} NV_ALIGN(4) NvRmDmaAbort_in;
+
+typedef struct NvRmDmaAbort_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaAbort_inout;
+
+typedef struct NvRmDmaAbort_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaAbort_out;
+
+typedef struct NvRmDmaAbort_params_t
+{
+    NvRmDmaAbort_in in;
+    NvRmDmaAbort_inout inout;
+    NvRmDmaAbort_out out;
+} NvRmDmaAbort_params;
+
+typedef struct NvRmDmaStartDmaTransfer_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDmaHandle hDma;
+    NvRmDmaClientBuffer pClientBuffer;
+    NvRmDmaDirection DmaDirection;
+    NvU32 WaitTimeoutInMilliSecond;
+    NvOsSemaphoreHandle AsynchSemaphoreId;
+} NV_ALIGN(4) NvRmDmaStartDmaTransfer_in;
+
+typedef struct NvRmDmaStartDmaTransfer_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaStartDmaTransfer_inout;
+
+typedef struct NvRmDmaStartDmaTransfer_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDmaStartDmaTransfer_out;
+
+typedef struct NvRmDmaStartDmaTransfer_params_t
+{
+    NvRmDmaStartDmaTransfer_in in;
+    NvRmDmaStartDmaTransfer_inout inout;
+    NvRmDmaStartDmaTransfer_out out;
+} NvRmDmaStartDmaTransfer_params;
+
+typedef struct NvRmDmaFree_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDmaHandle hDma;
+} NV_ALIGN(4) NvRmDmaFree_in;
+
+typedef struct NvRmDmaFree_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaFree_inout;
+
+typedef struct NvRmDmaFree_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaFree_out;
+
+typedef struct NvRmDmaFree_params_t
+{
+    NvRmDmaFree_in in;
+    NvRmDmaFree_inout inout;
+    NvRmDmaFree_out out;
+} NvRmDmaFree_params;
+
+typedef struct NvRmDmaAllocate_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvBool Enable32bitSwap;
+    NvRmDmaPriority Priority;
+    NvRmDmaModuleID DmaRequestorModuleId;
+    NvU32 DmaRequestorInstanceId;
+} NV_ALIGN(4) NvRmDmaAllocate_in;
+
+typedef struct NvRmDmaAllocate_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaAllocate_inout;
+
+typedef struct NvRmDmaAllocate_out_t
+{
+    NvError ret_;
+    NvRmDmaHandle phDma;
+} NV_ALIGN(4) NvRmDmaAllocate_out;
+
+typedef struct NvRmDmaAllocate_params_t
+{
+    NvRmDmaAllocate_in in;
+    NvRmDmaAllocate_inout inout;
+    NvRmDmaAllocate_out out;
+} NvRmDmaAllocate_params;
+
+typedef struct NvRmDmaGetCapabilities_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmDmaCapabilities pRmDmaCaps;
+} NV_ALIGN(4) NvRmDmaGetCapabilities_in;
+
+typedef struct NvRmDmaGetCapabilities_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaGetCapabilities_inout;
+
+typedef struct NvRmDmaGetCapabilities_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDmaGetCapabilities_out;
+
+typedef struct NvRmDmaGetCapabilities_params_t
+{
+    NvRmDmaGetCapabilities_in in;
+    NvRmDmaGetCapabilities_inout inout;
+    NvRmDmaGetCapabilities_out out;
+} NvRmDmaGetCapabilities_params;
+
+static NvError NvRmDmaIsDmaTransferCompletes_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaIsDmaTransferCompletes_in *p_in;
+    NvRmDmaIsDmaTransferCompletes_out *p_out;
+
+    p_in = (NvRmDmaIsDmaTransferCompletes_in *)InBuffer;
+    p_out = (NvRmDmaIsDmaTransferCompletes_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDmaIsDmaTransferCompletes_params, out) - OFFSET(NvRmDmaIsDmaTransferCompletes_params, inout));
+
+
+    p_out->ret_ = NvRmDmaIsDmaTransferCompletes( p_in->hDma, p_in->IsFirstHalfBuffer );
+
+    return err_;
+}
+
+static NvError NvRmDmaGetTransferredCount_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaGetTransferredCount_in *p_in;
+    NvRmDmaGetTransferredCount_out *p_out;
+
+    p_in = (NvRmDmaGetTransferredCount_in *)InBuffer;
+    p_out = (NvRmDmaGetTransferredCount_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDmaGetTransferredCount_params, out) - OFFSET(NvRmDmaGetTransferredCount_params, inout));
+
+
+    p_out->ret_ = NvRmDmaGetTransferredCount( p_in->hDma, &p_out->pTransferCount, p_in->IsTransferStop );
+
+    return err_;
+}
+
+static NvError NvRmDmaAbort_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaAbort_in *p_in;
+
+    p_in = (NvRmDmaAbort_in *)InBuffer;
+
+
+    NvRmDmaAbort( p_in->hDma );
+
+    return err_;
+}
+
+static NvError NvRmDmaStartDmaTransfer_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaStartDmaTransfer_in *p_in;
+    NvRmDmaStartDmaTransfer_out *p_out;
+    NvOsSemaphoreHandle AsynchSemaphoreId = NULL;
+
+    p_in = (NvRmDmaStartDmaTransfer_in *)InBuffer;
+    p_out = (NvRmDmaStartDmaTransfer_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDmaStartDmaTransfer_params, out) - OFFSET(NvRmDmaStartDmaTransfer_params, inout));
+
+    if( p_in->AsynchSemaphoreId )
+    {
+        err_ = NvOsSemaphoreUnmarshal( p_in->AsynchSemaphoreId, &AsynchSemaphoreId );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDmaStartDmaTransfer( p_in->hDma, &p_in->pClientBuffer, p_in->DmaDirection, p_in->WaitTimeoutInMilliSecond, AsynchSemaphoreId );
+
+clean:
+    NvOsSemaphoreDestroy( AsynchSemaphoreId );
+    return err_;
+}
+
+static NvError NvRmDmaFree_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaFree_in *p_in;
+
+    p_in = (NvRmDmaFree_in *)InBuffer;
+
+
+    NvRmDmaFree( p_in->hDma );
+
+    return err_;
+}
+
+static NvError NvRmDmaAllocate_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaAllocate_in *p_in;
+    NvRmDmaAllocate_out *p_out;
+
+    p_in = (NvRmDmaAllocate_in *)InBuffer;
+    p_out = (NvRmDmaAllocate_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDmaAllocate_params, out) - OFFSET(NvRmDmaAllocate_params, inout));
+
+
+    p_out->ret_ = NvRmDmaAllocate( p_in->hRmDevice, &p_out->phDma, p_in->Enable32bitSwap, p_in->Priority, p_in->DmaRequestorModuleId, p_in->DmaRequestorInstanceId );
+
+    return err_;
+}
+
+static NvError NvRmDmaGetCapabilities_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaGetCapabilities_in *p_in;
+    NvRmDmaGetCapabilities_out *p_out;
+
+    p_in = (NvRmDmaGetCapabilities_in *)InBuffer;
+    p_out = (NvRmDmaGetCapabilities_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDmaGetCapabilities_params, out) - OFFSET(NvRmDmaGetCapabilities_params, inout));
+
+
+    p_out->ret_ = NvRmDmaGetCapabilities( p_in->hDevice, &p_in->pRmDmaCaps );
+
+    return err_;
+}
+
+NvError nvrm_dma_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_dma_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 6:
+        err_ = NvRmDmaIsDmaTransferCompletes_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmDmaGetTransferredCount_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmDmaAbort_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmDmaStartDmaTransfer_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmDmaFree_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmDmaAllocate_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmDmaGetCapabilities_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_gpio_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_gpio_dispatch.c
new file mode 100644
index 000000000000..d932c98db502
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_gpio_dispatch.c
@@ -0,0 +1,566 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_gpio.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmGpioGetIrqs_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmGpioPinHandle  * pin;
+    NvU32  * Irq;
+    NvU32 pinCount;
+} NV_ALIGN(4) NvRmGpioGetIrqs_in;
+
+typedef struct NvRmGpioGetIrqs_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioGetIrqs_inout;
+
+typedef struct NvRmGpioGetIrqs_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmGpioGetIrqs_out;
+
+typedef struct NvRmGpioGetIrqs_params_t
+{
+    NvRmGpioGetIrqs_in in;
+    NvRmGpioGetIrqs_inout inout;
+    NvRmGpioGetIrqs_out out;
+} NvRmGpioGetIrqs_params;
+
+typedef struct NvRmGpioConfigPins_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+    NvRmGpioPinHandle  * pin;
+    NvU32 pinCount;
+    NvRmGpioPinMode Mode;
+} NV_ALIGN(4) NvRmGpioConfigPins_in;
+
+typedef struct NvRmGpioConfigPins_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioConfigPins_inout;
+
+typedef struct NvRmGpioConfigPins_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmGpioConfigPins_out;
+
+typedef struct NvRmGpioConfigPins_params_t
+{
+    NvRmGpioConfigPins_in in;
+    NvRmGpioConfigPins_inout inout;
+    NvRmGpioConfigPins_out out;
+} NvRmGpioConfigPins_params;
+
+typedef struct NvRmGpioReadPins_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+    NvRmGpioPinHandle  * pin;
+    NvRmGpioPinState  * pPinState;
+    NvU32 pinCount;
+} NV_ALIGN(4) NvRmGpioReadPins_in;
+
+typedef struct NvRmGpioReadPins_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioReadPins_inout;
+
+typedef struct NvRmGpioReadPins_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioReadPins_out;
+
+typedef struct NvRmGpioReadPins_params_t
+{
+    NvRmGpioReadPins_in in;
+    NvRmGpioReadPins_inout inout;
+    NvRmGpioReadPins_out out;
+} NvRmGpioReadPins_params;
+
+typedef struct NvRmGpioWritePins_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+    NvRmGpioPinHandle  * pin;
+    NvRmGpioPinState  * pinState;
+    NvU32 pinCount;
+} NV_ALIGN(4) NvRmGpioWritePins_in;
+
+typedef struct NvRmGpioWritePins_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioWritePins_inout;
+
+typedef struct NvRmGpioWritePins_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioWritePins_out;
+
+typedef struct NvRmGpioWritePins_params_t
+{
+    NvRmGpioWritePins_in in;
+    NvRmGpioWritePins_inout inout;
+    NvRmGpioWritePins_out out;
+} NvRmGpioWritePins_params;
+
+typedef struct NvRmGpioReleasePinHandles_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+    NvRmGpioPinHandle  * hPin;
+    NvU32 pinCount;
+} NV_ALIGN(4) NvRmGpioReleasePinHandles_in;
+
+typedef struct NvRmGpioReleasePinHandles_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioReleasePinHandles_inout;
+
+typedef struct NvRmGpioReleasePinHandles_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioReleasePinHandles_out;
+
+typedef struct NvRmGpioReleasePinHandles_params_t
+{
+    NvRmGpioReleasePinHandles_in in;
+    NvRmGpioReleasePinHandles_inout inout;
+    NvRmGpioReleasePinHandles_out out;
+} NvRmGpioReleasePinHandles_params;
+
+typedef struct NvRmGpioAcquirePinHandle_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+    NvU32 port;
+    NvU32 pin;
+} NV_ALIGN(4) NvRmGpioAcquirePinHandle_in;
+
+typedef struct NvRmGpioAcquirePinHandle_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioAcquirePinHandle_inout;
+
+typedef struct NvRmGpioAcquirePinHandle_out_t
+{
+    NvError ret_;
+    NvRmGpioPinHandle phPin;
+} NV_ALIGN(4) NvRmGpioAcquirePinHandle_out;
+
+typedef struct NvRmGpioAcquirePinHandle_params_t
+{
+    NvRmGpioAcquirePinHandle_in in;
+    NvRmGpioAcquirePinHandle_inout inout;
+    NvRmGpioAcquirePinHandle_out out;
+} NvRmGpioAcquirePinHandle_params;
+
+typedef struct NvRmGpioClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+} NV_ALIGN(4) NvRmGpioClose_in;
+
+typedef struct NvRmGpioClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioClose_inout;
+
+typedef struct NvRmGpioClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioClose_out;
+
+typedef struct NvRmGpioClose_params_t
+{
+    NvRmGpioClose_in in;
+    NvRmGpioClose_inout inout;
+    NvRmGpioClose_out out;
+} NvRmGpioClose_params;
+
+typedef struct NvRmGpioOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmGpioOpen_in;
+
+typedef struct NvRmGpioOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioOpen_inout;
+
+typedef struct NvRmGpioOpen_out_t
+{
+    NvError ret_;
+    NvRmGpioHandle phGpio;
+} NV_ALIGN(4) NvRmGpioOpen_out;
+
+typedef struct NvRmGpioOpen_params_t
+{
+    NvRmGpioOpen_in in;
+    NvRmGpioOpen_inout inout;
+    NvRmGpioOpen_out out;
+} NvRmGpioOpen_params;
+
+static NvError NvRmGpioGetIrqs_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioGetIrqs_in *p_in;
+    NvRmGpioGetIrqs_out *p_out;
+    NvRmGpioPinHandle *pin = NULL;
+    NvU32  *Irq = NULL;
+
+    p_in = (NvRmGpioGetIrqs_in *)InBuffer;
+    p_out = (NvRmGpioGetIrqs_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGpioGetIrqs_params, out) - OFFSET(NvRmGpioGetIrqs_params, inout));
+
+    if( p_in->pinCount && p_in->pin )
+    {
+        pin = (NvRmGpioPinHandle  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+        if( !pin )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pin )
+        {
+            err_ = NvOsCopyIn( pin, p_in->pin, p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->pinCount && p_in->Irq )
+    {
+        Irq = (NvU32  *)NvOsAlloc( p_in->pinCount * sizeof( NvU32  ) );
+        if( !Irq )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmGpioGetIrqs( p_in->hRmDevice, pin, Irq, p_in->pinCount );
+
+    if(p_in->Irq && Irq)
+    {
+        err_ = NvOsCopyOut( p_in->Irq, Irq, p_in->pinCount * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pin );
+    NvOsFree( Irq );
+    return err_;
+}
+
+static NvError NvRmGpioConfigPins_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioConfigPins_in *p_in;
+    NvRmGpioConfigPins_out *p_out;
+    NvRmGpioPinHandle *pin = NULL;
+
+    p_in = (NvRmGpioConfigPins_in *)InBuffer;
+    p_out = (NvRmGpioConfigPins_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGpioConfigPins_params, out) - OFFSET(NvRmGpioConfigPins_params, inout));
+
+    if( p_in->pinCount && p_in->pin )
+    {
+        pin = (NvRmGpioPinHandle  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+        if( !pin )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pin )
+        {
+            err_ = NvOsCopyIn( pin, p_in->pin, p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmGpioConfigPins( p_in->hGpio, pin, p_in->pinCount, p_in->Mode );
+
+clean:
+    NvOsFree( pin );
+    return err_;
+}
+
+static NvError NvRmGpioReadPins_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioReadPins_in *p_in;
+    NvRmGpioPinHandle *pin = NULL;
+    NvRmGpioPinState *pPinState = NULL;
+
+    p_in = (NvRmGpioReadPins_in *)InBuffer;
+
+    if( p_in->pinCount && p_in->pin )
+    {
+        pin = (NvRmGpioPinHandle  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+        if( !pin )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pin )
+        {
+            err_ = NvOsCopyIn( pin, p_in->pin, p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->pinCount && p_in->pPinState )
+    {
+        pPinState = (NvRmGpioPinState  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinState  ) );
+        if( !pPinState )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    NvRmGpioReadPins( p_in->hGpio, pin, pPinState, p_in->pinCount );
+
+    if(p_in->pPinState && pPinState)
+    {
+        err_ = NvOsCopyOut( p_in->pPinState, pPinState, p_in->pinCount * sizeof( NvRmGpioPinState  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pin );
+    NvOsFree( pPinState );
+    return err_;
+}
+
+static NvError NvRmGpioWritePins_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioWritePins_in *p_in;
+    NvRmGpioPinHandle *pin = NULL;
+    NvRmGpioPinState *pinState = NULL;
+
+    p_in = (NvRmGpioWritePins_in *)InBuffer;
+
+    if( p_in->pinCount && p_in->pin )
+    {
+        pin = (NvRmGpioPinHandle  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+        if( !pin )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pin )
+        {
+            err_ = NvOsCopyIn( pin, p_in->pin, p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->pinCount && p_in->pinState )
+    {
+        pinState = (NvRmGpioPinState  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinState  ) );
+        if( !pinState )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pinState )
+        {
+            err_ = NvOsCopyIn( pinState, p_in->pinState, p_in->pinCount * sizeof( NvRmGpioPinState  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRmGpioWritePins( p_in->hGpio, pin, pinState, p_in->pinCount );
+
+clean:
+    NvOsFree( pin );
+    NvOsFree( pinState );
+    return err_;
+}
+
+static NvError NvRmGpioReleasePinHandles_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioReleasePinHandles_in *p_in;
+    NvRmGpioPinHandle *hPin = NULL;
+
+    p_in = (NvRmGpioReleasePinHandles_in *)InBuffer;
+
+    if( p_in->pinCount && p_in->hPin )
+    {
+        hPin = (NvRmGpioPinHandle  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+        if( !hPin )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->hPin )
+        {
+            err_ = NvOsCopyIn( hPin, p_in->hPin, p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRmGpioReleasePinHandles( p_in->hGpio, hPin, p_in->pinCount );
+
+clean:
+    NvOsFree( hPin );
+    return err_;
+}
+
+static NvError NvRmGpioAcquirePinHandle_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioAcquirePinHandle_in *p_in;
+    NvRmGpioAcquirePinHandle_out *p_out;
+
+    p_in = (NvRmGpioAcquirePinHandle_in *)InBuffer;
+    p_out = (NvRmGpioAcquirePinHandle_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGpioAcquirePinHandle_params, out) - OFFSET(NvRmGpioAcquirePinHandle_params, inout));
+
+
+    p_out->ret_ = NvRmGpioAcquirePinHandle( p_in->hGpio, p_in->port, p_in->pin, &p_out->phPin );
+
+    return err_;
+}
+
+static NvError NvRmGpioClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioClose_in *p_in;
+
+    p_in = (NvRmGpioClose_in *)InBuffer;
+
+
+    NvRmGpioClose( p_in->hGpio );
+
+    return err_;
+}
+
+static NvError NvRmGpioOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioOpen_in *p_in;
+    NvRmGpioOpen_out *p_out;
+
+    p_in = (NvRmGpioOpen_in *)InBuffer;
+    p_out = (NvRmGpioOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGpioOpen_params, out) - OFFSET(NvRmGpioOpen_params, inout));
+
+
+    p_out->ret_ = NvRmGpioOpen( p_in->hRmDevice, &p_out->phGpio );
+
+    return err_;
+}
+
+NvError nvrm_gpio_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_gpio_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 7:
+        err_ = NvRmGpioGetIrqs_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmGpioConfigPins_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmGpioReadPins_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmGpioWritePins_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmGpioReleasePinHandles_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmGpioAcquirePinHandle_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmGpioClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmGpioOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_i2c_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_i2c_dispatch.c
new file mode 100644
index 000000000000..6e2672dff896
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_i2c_dispatch.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_i2c.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmI2cTransaction_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmI2cHandle hI2c;
+    NvU32 I2cPinMap;
+    NvU32 WaitTimeoutInMilliSeconds;
+    NvU32 ClockSpeedKHz;
+    NvU8  * Data;
+    NvU32 DataLen;
+    NvRmI2cTransactionInfo  * Transaction;
+    NvU32 NumOfTransactions;
+} NV_ALIGN(4) NvRmI2cTransaction_in;
+
+typedef struct NvRmI2cTransaction_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmI2cTransaction_inout;
+
+typedef struct NvRmI2cTransaction_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmI2cTransaction_out;
+
+typedef struct NvRmI2cTransaction_params_t
+{
+    NvRmI2cTransaction_in in;
+    NvRmI2cTransaction_inout inout;
+    NvRmI2cTransaction_out out;
+} NvRmI2cTransaction_params;
+
+typedef struct NvRmI2cClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmI2cHandle hI2c;
+} NV_ALIGN(4) NvRmI2cClose_in;
+
+typedef struct NvRmI2cClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmI2cClose_inout;
+
+typedef struct NvRmI2cClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmI2cClose_out;
+
+typedef struct NvRmI2cClose_params_t
+{
+    NvRmI2cClose_in in;
+    NvRmI2cClose_inout inout;
+    NvRmI2cClose_out out;
+} NvRmI2cClose_params;
+
+typedef struct NvRmI2cOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 IoModule;
+    NvU32 instance;
+} NV_ALIGN(4) NvRmI2cOpen_in;
+
+typedef struct NvRmI2cOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmI2cOpen_inout;
+
+typedef struct NvRmI2cOpen_out_t
+{
+    NvError ret_;
+    NvRmI2cHandle phI2c;
+} NV_ALIGN(4) NvRmI2cOpen_out;
+
+typedef struct NvRmI2cOpen_params_t
+{
+    NvRmI2cOpen_in in;
+    NvRmI2cOpen_inout inout;
+    NvRmI2cOpen_out out;
+} NvRmI2cOpen_params;
+
+static NvError NvRmI2cTransaction_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmI2cTransaction_in *p_in;
+    NvRmI2cTransaction_out *p_out;
+    NvU8  *Data = NULL;
+    NvRmI2cTransactionInfo *Transaction = NULL;
+
+    p_in = (NvRmI2cTransaction_in *)InBuffer;
+    p_out = (NvRmI2cTransaction_out *)((NvU8 *)OutBuffer + OFFSET(NvRmI2cTransaction_params, out) - OFFSET(NvRmI2cTransaction_params, inout));
+
+    if( p_in->DataLen && p_in->Data )
+    {
+        Data = (NvU8  *)NvOsAlloc( p_in->DataLen * sizeof( NvU8  ) );
+        if( !Data )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Data )
+        {
+            err_ = NvOsCopyIn( Data, p_in->Data, p_in->DataLen * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->NumOfTransactions && p_in->Transaction )
+    {
+        Transaction = (NvRmI2cTransactionInfo  *)NvOsAlloc( p_in->NumOfTransactions * sizeof( NvRmI2cTransactionInfo  ) );
+        if( !Transaction )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Transaction )
+        {
+            err_ = NvOsCopyIn( Transaction, p_in->Transaction, p_in->NumOfTransactions * sizeof( NvRmI2cTransactionInfo  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmI2cTransaction( p_in->hI2c, p_in->I2cPinMap, p_in->WaitTimeoutInMilliSeconds, p_in->ClockSpeedKHz, Data, p_in->DataLen, Transaction, p_in->NumOfTransactions );
+
+    if(p_in->Data && Data)
+    {
+        err_ = NvOsCopyOut( p_in->Data, Data, p_in->DataLen * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( Data );
+    NvOsFree( Transaction );
+    return err_;
+}
+
+static NvError NvRmI2cClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmI2cClose_in *p_in;
+
+    p_in = (NvRmI2cClose_in *)InBuffer;
+
+
+    NvRmI2cClose( p_in->hI2c );
+
+    return err_;
+}
+
+static NvError NvRmI2cOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmI2cOpen_in *p_in;
+    NvRmI2cOpen_out *p_out;
+
+    p_in = (NvRmI2cOpen_in *)InBuffer;
+    p_out = (NvRmI2cOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmI2cOpen_params, out) - OFFSET(NvRmI2cOpen_params, inout));
+
+
+    p_out->ret_ = NvRmI2cOpen( p_in->hDevice, p_in->IoModule, p_in->instance, &p_out->phI2c );
+
+    return err_;
+}
+
+NvError nvrm_i2c_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_i2c_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 2:
+        err_ = NvRmI2cTransaction_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmI2cClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmI2cOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_init_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_init_dispatch.c
new file mode 100644
index 000000000000..1c438a100957
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_init_dispatch.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_init.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmClose_in;
+
+typedef struct NvRmClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmClose_inout;
+
+typedef struct NvRmClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmClose_out;
+
+typedef struct NvRmClose_params_t
+{
+    NvRmClose_in in;
+    NvRmClose_inout inout;
+    NvRmClose_out out;
+} NvRmClose_params;
+
+typedef struct NvRmOpenNew_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+} NV_ALIGN(4) NvRmOpenNew_in;
+
+typedef struct NvRmOpenNew_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOpenNew_inout;
+
+typedef struct NvRmOpenNew_out_t
+{
+    NvError ret_;
+    NvRmDeviceHandle pHandle;
+} NV_ALIGN(4) NvRmOpenNew_out;
+
+typedef struct NvRmOpenNew_params_t
+{
+    NvRmOpenNew_in in;
+    NvRmOpenNew_inout inout;
+    NvRmOpenNew_out out;
+} NvRmOpenNew_params;
+
+typedef struct NvRmInit_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+} NV_ALIGN(4) NvRmInit_in;
+
+typedef struct NvRmInit_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmInit_inout;
+
+typedef struct NvRmInit_out_t
+{
+    NvRmDeviceHandle pHandle;
+} NV_ALIGN(4) NvRmInit_out;
+
+typedef struct NvRmInit_params_t
+{
+    NvRmInit_in in;
+    NvRmInit_inout inout;
+    NvRmInit_out out;
+} NvRmInit_params;
+
+typedef struct NvRmOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvU32 DeviceId;
+} NV_ALIGN(4) NvRmOpen_in;
+
+typedef struct NvRmOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOpen_inout;
+
+typedef struct NvRmOpen_out_t
+{
+    NvError ret_;
+    NvRmDeviceHandle pHandle;
+} NV_ALIGN(4) NvRmOpen_out;
+
+typedef struct NvRmOpen_params_t
+{
+    NvRmOpen_in in;
+    NvRmOpen_inout inout;
+    NvRmOpen_out out;
+} NvRmOpen_params;
+
+static NvError NvRmClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmClose_in *p_in;
+
+    p_in = (NvRmClose_in *)InBuffer;
+
+
+    NvRmClose( p_in->hDevice );
+
+    return err_;
+}
+
+static NvError NvRmOpenNew_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmOpenNew_in *p_in;
+    NvRmOpenNew_out *p_out;
+
+    p_in = (NvRmOpenNew_in *)InBuffer;
+    p_out = (NvRmOpenNew_out *)((NvU8 *)OutBuffer + OFFSET(NvRmOpenNew_params, out) - OFFSET(NvRmOpenNew_params, inout));
+
+
+    p_out->ret_ = NvRmOpenNew( &p_out->pHandle );
+
+    return err_;
+}
+
+static NvError NvRmInit_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmInit_in *p_in;
+    NvRmInit_out *p_out;
+
+    p_in = (NvRmInit_in *)InBuffer;
+    p_out = (NvRmInit_out *)((NvU8 *)OutBuffer + OFFSET(NvRmInit_params, out) - OFFSET(NvRmInit_params, inout));
+
+
+    NvRmInit( &p_out->pHandle );
+
+    return err_;
+}
+
+static NvError NvRmOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmOpen_in *p_in;
+    NvRmOpen_out *p_out;
+
+    p_in = (NvRmOpen_in *)InBuffer;
+    p_out = (NvRmOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmOpen_params, out) - OFFSET(NvRmOpen_params, inout));
+
+
+    p_out->ret_ = NvRmOpen( &p_out->pHandle, p_in->DeviceId );
+
+    return err_;
+}
+
+NvError nvrm_init_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_init_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 3:
+        err_ = NvRmClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmOpenNew_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmInit_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_interrupt_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_interrupt_dispatch.c
new file mode 100644
index 000000000000..007117333979
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_interrupt_dispatch.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_interrupt.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmGetIrqCountForLogicalInterrupt_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmModuleID ModuleID;
+} NV_ALIGN(4) NvRmGetIrqCountForLogicalInterrupt_in;
+
+typedef struct NvRmGetIrqCountForLogicalInterrupt_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetIrqCountForLogicalInterrupt_inout;
+
+typedef struct NvRmGetIrqCountForLogicalInterrupt_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmGetIrqCountForLogicalInterrupt_out;
+
+typedef struct NvRmGetIrqCountForLogicalInterrupt_params_t
+{
+    NvRmGetIrqCountForLogicalInterrupt_in in;
+    NvRmGetIrqCountForLogicalInterrupt_inout inout;
+    NvRmGetIrqCountForLogicalInterrupt_out out;
+} NvRmGetIrqCountForLogicalInterrupt_params;
+
+typedef struct NvRmGetIrqForLogicalInterrupt_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmModuleID ModuleID;
+    NvU32 Index;
+} NV_ALIGN(4) NvRmGetIrqForLogicalInterrupt_in;
+
+typedef struct NvRmGetIrqForLogicalInterrupt_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetIrqForLogicalInterrupt_inout;
+
+typedef struct NvRmGetIrqForLogicalInterrupt_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmGetIrqForLogicalInterrupt_out;
+
+typedef struct NvRmGetIrqForLogicalInterrupt_params_t
+{
+    NvRmGetIrqForLogicalInterrupt_in in;
+    NvRmGetIrqForLogicalInterrupt_inout inout;
+    NvRmGetIrqForLogicalInterrupt_out out;
+} NvRmGetIrqForLogicalInterrupt_params;
+
+static NvError NvRmGetIrqCountForLogicalInterrupt_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetIrqCountForLogicalInterrupt_in *p_in;
+    NvRmGetIrqCountForLogicalInterrupt_out *p_out;
+
+    p_in = (NvRmGetIrqCountForLogicalInterrupt_in *)InBuffer;
+    p_out = (NvRmGetIrqCountForLogicalInterrupt_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetIrqCountForLogicalInterrupt_params, out) - OFFSET(NvRmGetIrqCountForLogicalInterrupt_params, inout));
+
+
+    p_out->ret_ = NvRmGetIrqCountForLogicalInterrupt( p_in->hRmDevice, p_in->ModuleID );
+
+    return err_;
+}
+
+static NvError NvRmGetIrqForLogicalInterrupt_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetIrqForLogicalInterrupt_in *p_in;
+    NvRmGetIrqForLogicalInterrupt_out *p_out;
+
+    p_in = (NvRmGetIrqForLogicalInterrupt_in *)InBuffer;
+    p_out = (NvRmGetIrqForLogicalInterrupt_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetIrqForLogicalInterrupt_params, out) - OFFSET(NvRmGetIrqForLogicalInterrupt_params, inout));
+
+
+    p_out->ret_ = NvRmGetIrqForLogicalInterrupt( p_in->hRmDevice, p_in->ModuleID, p_in->Index );
+
+    return err_;
+}
+
+NvError nvrm_interrupt_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_interrupt_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 1:
+        err_ = NvRmGetIrqCountForLogicalInterrupt_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmGetIrqForLogicalInterrupt_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_keylist_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_keylist_dispatch.c
new file mode 100644
index 000000000000..4e242392cd4a
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_keylist_dispatch.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_keylist.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmSetKeyValuePair_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRm;
+    NvU32 KeyID;
+    NvU32 Value;
+} NV_ALIGN(4) NvRmSetKeyValuePair_in;
+
+typedef struct NvRmSetKeyValuePair_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSetKeyValuePair_inout;
+
+typedef struct NvRmSetKeyValuePair_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmSetKeyValuePair_out;
+
+typedef struct NvRmSetKeyValuePair_params_t
+{
+    NvRmSetKeyValuePair_in in;
+    NvRmSetKeyValuePair_inout inout;
+    NvRmSetKeyValuePair_out out;
+} NvRmSetKeyValuePair_params;
+
+typedef struct NvRmGetKeyValue_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRm;
+    NvU32 KeyID;
+} NV_ALIGN(4) NvRmGetKeyValue_in;
+
+typedef struct NvRmGetKeyValue_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetKeyValue_inout;
+
+typedef struct NvRmGetKeyValue_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmGetKeyValue_out;
+
+typedef struct NvRmGetKeyValue_params_t
+{
+    NvRmGetKeyValue_in in;
+    NvRmGetKeyValue_inout inout;
+    NvRmGetKeyValue_out out;
+} NvRmGetKeyValue_params;
+
+static NvError NvRmSetKeyValuePair_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSetKeyValuePair_in *p_in;
+    NvRmSetKeyValuePair_out *p_out;
+
+    p_in = (NvRmSetKeyValuePair_in *)InBuffer;
+    p_out = (NvRmSetKeyValuePair_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSetKeyValuePair_params, out) - OFFSET(NvRmSetKeyValuePair_params, inout));
+
+
+    p_out->ret_ = NvRmSetKeyValuePair( p_in->hRm, p_in->KeyID, p_in->Value );
+
+    return err_;
+}
+
+static NvError NvRmGetKeyValue_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetKeyValue_in *p_in;
+    NvRmGetKeyValue_out *p_out;
+
+    p_in = (NvRmGetKeyValue_in *)InBuffer;
+    p_out = (NvRmGetKeyValue_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetKeyValue_params, out) - OFFSET(NvRmGetKeyValue_params, inout));
+
+
+    p_out->ret_ = NvRmGetKeyValue( p_in->hRm, p_in->KeyID );
+
+    return err_;
+}
+
+NvError nvrm_keylist_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_keylist_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 1:
+        err_ = NvRmSetKeyValuePair_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmGetKeyValue_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_memctrl_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_memctrl_dispatch.c
new file mode 100644
index 000000000000..b2a4f77a8f67
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_memctrl_dispatch.c
@@ -0,0 +1,383 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_memctrl.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmCorePerfMonStop_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvU32  * pCountList;
+} NV_ALIGN(4) NvRmCorePerfMonStop_in;
+
+typedef struct NvRmCorePerfMonStop_inout_t
+{
+    NvU32 pCountListSize;
+} NV_ALIGN(4) NvRmCorePerfMonStop_inout;
+
+typedef struct NvRmCorePerfMonStop_out_t
+{
+    NvError ret_;
+    NvU32 pTotalCycleCount;
+} NV_ALIGN(4) NvRmCorePerfMonStop_out;
+
+typedef struct NvRmCorePerfMonStop_params_t
+{
+    NvRmCorePerfMonStop_in in;
+    NvRmCorePerfMonStop_inout inout;
+    NvRmCorePerfMonStop_out out;
+} NvRmCorePerfMonStop_params;
+
+typedef struct NvRmCorePerfMonStart_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvU32  * pEventList;
+} NV_ALIGN(4) NvRmCorePerfMonStart_in;
+
+typedef struct NvRmCorePerfMonStart_inout_t
+{
+    NvU32 pEventListSize;
+} NV_ALIGN(4) NvRmCorePerfMonStart_inout;
+
+typedef struct NvRmCorePerfMonStart_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmCorePerfMonStart_out;
+
+typedef struct NvRmCorePerfMonStart_params_t
+{
+    NvRmCorePerfMonStart_in in;
+    NvRmCorePerfMonStart_inout inout;
+    NvRmCorePerfMonStart_out out;
+} NvRmCorePerfMonStart_params;
+
+typedef struct ReadObsData_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle rm;
+    NvRmModuleID modId;
+    NvU32 start_index;
+    NvU32 length;
+} NV_ALIGN(4) ReadObsData_in;
+
+typedef struct ReadObsData_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) ReadObsData_inout;
+
+typedef struct ReadObsData_out_t
+{
+    NvError ret_;
+    NvU32 value;
+} NV_ALIGN(4) ReadObsData_out;
+
+typedef struct ReadObsData_params_t
+{
+    ReadObsData_in in;
+    ReadObsData_inout inout;
+    ReadObsData_out out;
+} ReadObsData_params;
+
+typedef struct McStat_Report_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvU32 client_id_0;
+    NvU32 client_0_cycles;
+    NvU32 client_id_1;
+    NvU32 client_1_cycles;
+    NvU32 llc_client_id;
+    NvU32 llc_client_clocks;
+    NvU32 llc_client_cycles;
+    NvU32 mc_clocks;
+} NV_ALIGN(4) McStat_Report_in;
+
+typedef struct McStat_Report_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) McStat_Report_inout;
+
+typedef struct McStat_Report_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) McStat_Report_out;
+
+typedef struct McStat_Report_params_t
+{
+    McStat_Report_in in;
+    McStat_Report_inout inout;
+    McStat_Report_out out;
+} McStat_Report_params;
+
+typedef struct McStat_Stop_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle rm;
+} NV_ALIGN(4) McStat_Stop_in;
+
+typedef struct McStat_Stop_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) McStat_Stop_inout;
+
+typedef struct McStat_Stop_out_t
+{
+    NvU32 client_0_cycles;
+    NvU32 client_1_cycles;
+    NvU32 llc_client_cycles;
+    NvU32 llc_client_clocks;
+    NvU32 mc_clocks;
+} NV_ALIGN(4) McStat_Stop_out;
+
+typedef struct McStat_Stop_params_t
+{
+    McStat_Stop_in in;
+    McStat_Stop_inout inout;
+    McStat_Stop_out out;
+} McStat_Stop_params;
+
+typedef struct McStat_Start_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle rm;
+    NvU32 client_id_0;
+    NvU32 client_id_1;
+    NvU32 llc_client_id;
+} NV_ALIGN(4) McStat_Start_in;
+
+typedef struct McStat_Start_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) McStat_Start_inout;
+
+typedef struct McStat_Start_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) McStat_Start_out;
+
+typedef struct McStat_Start_params_t
+{
+    McStat_Start_in in;
+    McStat_Start_inout inout;
+    McStat_Start_out out;
+} McStat_Start_params;
+
+static NvError NvRmCorePerfMonStop_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmCorePerfMonStop_in *p_in;
+    NvRmCorePerfMonStop_inout *p_inout;
+    NvRmCorePerfMonStop_out *p_out;
+    NvRmCorePerfMonStop_inout inout;
+    NvU32  *pCountList = NULL;
+
+    p_in = (NvRmCorePerfMonStop_in *)InBuffer;
+    p_inout = (NvRmCorePerfMonStop_inout *)((NvU8 *)InBuffer + OFFSET(NvRmCorePerfMonStop_params, inout));
+    p_out = (NvRmCorePerfMonStop_out *)((NvU8 *)OutBuffer + OFFSET(NvRmCorePerfMonStop_params, out) - OFFSET(NvRmCorePerfMonStop_params, inout));
+
+    (void)inout;
+    inout.pCountListSize = p_inout->pCountListSize;
+    if( p_inout->pCountListSize && p_in->pCountList )
+    {
+        pCountList = (NvU32  *)NvOsAlloc( p_inout->pCountListSize * sizeof( NvU32  ) );
+        if( !pCountList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmCorePerfMonStop( p_in->hRmDevice, &inout.pCountListSize, pCountList, &p_out->pTotalCycleCount );
+
+
+    p_inout = (NvRmCorePerfMonStop_inout *)OutBuffer;
+    p_inout->pCountListSize = inout.pCountListSize;
+    if(p_in->pCountList && pCountList)
+    {
+        err_ = NvOsCopyOut( p_in->pCountList, pCountList, p_inout->pCountListSize * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pCountList );
+    return err_;
+}
+
+static NvError NvRmCorePerfMonStart_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmCorePerfMonStart_in *p_in;
+    NvRmCorePerfMonStart_inout *p_inout;
+    NvRmCorePerfMonStart_out *p_out;
+    NvRmCorePerfMonStart_inout inout;
+    NvU32  *pEventList = NULL;
+
+    p_in = (NvRmCorePerfMonStart_in *)InBuffer;
+    p_inout = (NvRmCorePerfMonStart_inout *)((NvU8 *)InBuffer + OFFSET(NvRmCorePerfMonStart_params, inout));
+    p_out = (NvRmCorePerfMonStart_out *)((NvU8 *)OutBuffer + OFFSET(NvRmCorePerfMonStart_params, out) - OFFSET(NvRmCorePerfMonStart_params, inout));
+
+    (void)inout;
+    inout.pEventListSize = p_inout->pEventListSize;
+    if( p_inout->pEventListSize && p_in->pEventList )
+    {
+        pEventList = (NvU32  *)NvOsAlloc( p_inout->pEventListSize * sizeof( NvU32  ) );
+        if( !pEventList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pEventList )
+        {
+            err_ = NvOsCopyIn( pEventList, p_in->pEventList, p_inout->pEventListSize * sizeof( NvU32  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmCorePerfMonStart( p_in->hRmDevice, &inout.pEventListSize, pEventList );
+
+
+    p_inout = (NvRmCorePerfMonStart_inout *)OutBuffer;
+    p_inout->pEventListSize = inout.pEventListSize;
+clean:
+    NvOsFree( pEventList );
+    return err_;
+}
+
+static NvError ReadObsData_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    ReadObsData_in *p_in;
+    ReadObsData_out *p_out;
+
+    p_in = (ReadObsData_in *)InBuffer;
+    p_out = (ReadObsData_out *)((NvU8 *)OutBuffer + OFFSET(ReadObsData_params, out) - OFFSET(ReadObsData_params, inout));
+
+
+    p_out->ret_ = ReadObsData( p_in->rm, p_in->modId, p_in->start_index, p_in->length, &p_out->value );
+
+    return err_;
+}
+
+static NvError McStat_Report_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    McStat_Report_in *p_in;
+
+    p_in = (McStat_Report_in *)InBuffer;
+
+
+    McStat_Report( p_in->client_id_0, p_in->client_0_cycles, p_in->client_id_1, p_in->client_1_cycles, p_in->llc_client_id, p_in->llc_client_clocks, p_in->llc_client_cycles, p_in->mc_clocks );
+
+    return err_;
+}
+
+static NvError McStat_Stop_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    McStat_Stop_in *p_in;
+    McStat_Stop_out *p_out;
+
+    p_in = (McStat_Stop_in *)InBuffer;
+    p_out = (McStat_Stop_out *)((NvU8 *)OutBuffer + OFFSET(McStat_Stop_params, out) - OFFSET(McStat_Stop_params, inout));
+
+
+    McStat_Stop( p_in->rm, &p_out->client_0_cycles, &p_out->client_1_cycles, &p_out->llc_client_cycles, &p_out->llc_client_clocks, &p_out->mc_clocks );
+
+    return err_;
+}
+
+static NvError McStat_Start_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    McStat_Start_in *p_in;
+
+    p_in = (McStat_Start_in *)InBuffer;
+
+
+    McStat_Start( p_in->rm, p_in->client_id_0, p_in->client_id_1, p_in->llc_client_id );
+
+    return err_;
+}
+
+NvError nvrm_memctrl_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_memctrl_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 5:
+        err_ = NvRmCorePerfMonStop_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmCorePerfMonStart_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = ReadObsData_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = McStat_Report_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = McStat_Stop_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = McStat_Start_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_memmgr_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_memmgr_dispatch.c
new file mode 100644
index 000000000000..57b08df02223
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_memmgr_dispatch.c
@@ -0,0 +1,941 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_memmgr.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmMemGetStat_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemStat Stat;
+} NV_ALIGN(4) NvRmMemGetStat_in;
+
+typedef struct NvRmMemGetStat_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetStat_inout;
+
+typedef struct NvRmMemGetStat_out_t
+{
+    NvError ret_;
+    NvS32 Result;
+} NV_ALIGN(4) NvRmMemGetStat_out;
+
+typedef struct NvRmMemGetStat_params_t
+{
+    NvRmMemGetStat_in in;
+    NvRmMemGetStat_inout inout;
+    NvRmMemGetStat_out out;
+} NvRmMemGetStat_params;
+
+typedef struct NvRmMemHandleFromId_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvU32 id;
+} NV_ALIGN(4) NvRmMemHandleFromId_in;
+
+typedef struct NvRmMemHandleFromId_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandleFromId_inout;
+
+typedef struct NvRmMemHandleFromId_out_t
+{
+    NvError ret_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemHandleFromId_out;
+
+typedef struct NvRmMemHandleFromId_params_t
+{
+    NvRmMemHandleFromId_in in;
+    NvRmMemHandleFromId_inout inout;
+    NvRmMemHandleFromId_out out;
+} NvRmMemHandleFromId_params;
+
+typedef struct NvRmMemGetId_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemGetId_in;
+
+typedef struct NvRmMemGetId_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetId_inout;
+
+typedef struct NvRmMemGetId_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemGetId_out;
+
+typedef struct NvRmMemGetId_params_t
+{
+    NvRmMemGetId_in in;
+    NvRmMemGetId_inout inout;
+    NvRmMemGetId_out out;
+} NvRmMemGetId_params;
+
+typedef struct NvRmMemGetHeapType_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemGetHeapType_in;
+
+typedef struct NvRmMemGetHeapType_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetHeapType_inout;
+
+typedef struct NvRmMemGetHeapType_out_t
+{
+    NvRmHeap ret_;
+    NvU32 BasePhysAddr;
+} NV_ALIGN(4) NvRmMemGetHeapType_out;
+
+typedef struct NvRmMemGetHeapType_params_t
+{
+    NvRmMemGetHeapType_in in;
+    NvRmMemGetHeapType_inout inout;
+    NvRmMemGetHeapType_out out;
+} NvRmMemGetHeapType_params;
+
+typedef struct NvRmMemGetCacheLineSize_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+} NV_ALIGN(4) NvRmMemGetCacheLineSize_in;
+
+typedef struct NvRmMemGetCacheLineSize_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetCacheLineSize_inout;
+
+typedef struct NvRmMemGetCacheLineSize_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemGetCacheLineSize_out;
+
+typedef struct NvRmMemGetCacheLineSize_params_t
+{
+    NvRmMemGetCacheLineSize_in in;
+    NvRmMemGetCacheLineSize_inout inout;
+    NvRmMemGetCacheLineSize_out out;
+} NvRmMemGetCacheLineSize_params;
+
+typedef struct NvRmMemGetAlignment_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemGetAlignment_in;
+
+typedef struct NvRmMemGetAlignment_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetAlignment_inout;
+
+typedef struct NvRmMemGetAlignment_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemGetAlignment_out;
+
+typedef struct NvRmMemGetAlignment_params_t
+{
+    NvRmMemGetAlignment_in in;
+    NvRmMemGetAlignment_inout inout;
+    NvRmMemGetAlignment_out out;
+} NvRmMemGetAlignment_params;
+
+typedef struct NvRmMemGetSize_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemGetSize_in;
+
+typedef struct NvRmMemGetSize_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetSize_inout;
+
+typedef struct NvRmMemGetSize_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemGetSize_out;
+
+typedef struct NvRmMemGetSize_params_t
+{
+    NvRmMemGetSize_in in;
+    NvRmMemGetSize_inout inout;
+    NvRmMemGetSize_out out;
+} NvRmMemGetSize_params;
+
+typedef struct NvRmMemMove_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hDstMem;
+    NvU32 DstOffset;
+    NvRmMemHandle hSrcMem;
+    NvU32 SrcOffset;
+    NvU32 Size;
+} NV_ALIGN(4) NvRmMemMove_in;
+
+typedef struct NvRmMemMove_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemMove_inout;
+
+typedef struct NvRmMemMove_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemMove_out;
+
+typedef struct NvRmMemMove_params_t
+{
+    NvRmMemMove_in in;
+    NvRmMemMove_inout inout;
+    NvRmMemMove_out out;
+} NvRmMemMove_params;
+
+typedef struct NvRmMemUnpinMult_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle  * hMems;
+    NvU32 Count;
+} NV_ALIGN(4) NvRmMemUnpinMult_in;
+
+typedef struct NvRmMemUnpinMult_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemUnpinMult_inout;
+
+typedef struct NvRmMemUnpinMult_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemUnpinMult_out;
+
+typedef struct NvRmMemUnpinMult_params_t
+{
+    NvRmMemUnpinMult_in in;
+    NvRmMemUnpinMult_inout inout;
+    NvRmMemUnpinMult_out out;
+} NvRmMemUnpinMult_params;
+
+typedef struct NvRmMemUnpin_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemUnpin_in;
+
+typedef struct NvRmMemUnpin_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemUnpin_inout;
+
+typedef struct NvRmMemUnpin_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemUnpin_out;
+
+typedef struct NvRmMemUnpin_params_t
+{
+    NvRmMemUnpin_in in;
+    NvRmMemUnpin_inout inout;
+    NvRmMemUnpin_out out;
+} NvRmMemUnpin_params;
+
+typedef struct NvRmMemGetAddress_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+    NvU32 Offset;
+} NV_ALIGN(4) NvRmMemGetAddress_in;
+
+typedef struct NvRmMemGetAddress_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetAddress_inout;
+
+typedef struct NvRmMemGetAddress_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemGetAddress_out;
+
+typedef struct NvRmMemGetAddress_params_t
+{
+    NvRmMemGetAddress_in in;
+    NvRmMemGetAddress_inout inout;
+    NvRmMemGetAddress_out out;
+} NvRmMemGetAddress_params;
+
+typedef struct NvRmMemPinMult_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle  * hMems;
+    NvU32  * Addrs;
+    NvU32 Count;
+} NV_ALIGN(4) NvRmMemPinMult_in;
+
+typedef struct NvRmMemPinMult_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemPinMult_inout;
+
+typedef struct NvRmMemPinMult_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemPinMult_out;
+
+typedef struct NvRmMemPinMult_params_t
+{
+    NvRmMemPinMult_in in;
+    NvRmMemPinMult_inout inout;
+    NvRmMemPinMult_out out;
+} NvRmMemPinMult_params;
+
+typedef struct NvRmMemPin_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemPin_in;
+
+typedef struct NvRmMemPin_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemPin_inout;
+
+typedef struct NvRmMemPin_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemPin_out;
+
+typedef struct NvRmMemPin_params_t
+{
+    NvRmMemPin_in in;
+    NvRmMemPin_inout inout;
+    NvRmMemPin_out out;
+} NvRmMemPin_params;
+
+typedef struct NvRmMemAlloc_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+    NvRmHeap  * Heaps;
+    NvU32 NumHeaps;
+    NvU32 Alignment;
+    NvOsMemAttribute Coherency;
+} NV_ALIGN(4) NvRmMemAlloc_in;
+
+typedef struct NvRmMemAlloc_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemAlloc_inout;
+
+typedef struct NvRmMemAlloc_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmMemAlloc_out;
+
+typedef struct NvRmMemAlloc_params_t
+{
+    NvRmMemAlloc_in in;
+    NvRmMemAlloc_inout inout;
+    NvRmMemAlloc_out out;
+} NvRmMemAlloc_params;
+
+typedef struct NvRmMemHandleFree_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemHandleFree_in;
+
+typedef struct NvRmMemHandleFree_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandleFree_inout;
+
+typedef struct NvRmMemHandleFree_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandleFree_out;
+
+typedef struct NvRmMemHandleFree_params_t
+{
+    NvRmMemHandleFree_in in;
+    NvRmMemHandleFree_inout inout;
+    NvRmMemHandleFree_out out;
+} NvRmMemHandleFree_params;
+
+typedef struct NvRmMemHandlePreserveHandle_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemHandlePreserveHandle_in;
+
+typedef struct NvRmMemHandlePreserveHandle_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandlePreserveHandle_inout;
+
+typedef struct NvRmMemHandlePreserveHandle_out_t
+{
+    NvError ret_;
+    NvU32 Key;
+} NV_ALIGN(4) NvRmMemHandlePreserveHandle_out;
+
+typedef struct NvRmMemHandlePreserveHandle_params_t
+{
+    NvRmMemHandlePreserveHandle_in in;
+    NvRmMemHandlePreserveHandle_inout inout;
+    NvRmMemHandlePreserveHandle_out out;
+} NvRmMemHandlePreserveHandle_params;
+
+typedef struct NvRmMemHandleClaimPreservedHandle_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 Key;
+} NV_ALIGN(4) NvRmMemHandleClaimPreservedHandle_in;
+
+typedef struct NvRmMemHandleClaimPreservedHandle_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandleClaimPreservedHandle_inout;
+
+typedef struct NvRmMemHandleClaimPreservedHandle_out_t
+{
+    NvError ret_;
+    NvRmMemHandle phMem;
+} NV_ALIGN(4) NvRmMemHandleClaimPreservedHandle_out;
+
+typedef struct NvRmMemHandleClaimPreservedHandle_params_t
+{
+    NvRmMemHandleClaimPreservedHandle_in in;
+    NvRmMemHandleClaimPreservedHandle_inout inout;
+    NvRmMemHandleClaimPreservedHandle_out out;
+} NvRmMemHandleClaimPreservedHandle_params;
+
+typedef struct NvRmMemHandleCreate_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 Size;
+} NV_ALIGN(4) NvRmMemHandleCreate_in;
+
+typedef struct NvRmMemHandleCreate_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandleCreate_inout;
+
+typedef struct NvRmMemHandleCreate_out_t
+{
+    NvError ret_;
+    NvRmMemHandle phMem;
+} NV_ALIGN(4) NvRmMemHandleCreate_out;
+
+typedef struct NvRmMemHandleCreate_params_t
+{
+    NvRmMemHandleCreate_in in;
+    NvRmMemHandleCreate_inout inout;
+    NvRmMemHandleCreate_out out;
+} NvRmMemHandleCreate_params;
+
+static NvError NvRmMemGetStat_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetStat_in *p_in;
+    NvRmMemGetStat_out *p_out;
+
+    p_in = (NvRmMemGetStat_in *)InBuffer;
+    p_out = (NvRmMemGetStat_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetStat_params, out) - OFFSET(NvRmMemGetStat_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetStat( p_in->Stat, &p_out->Result );
+
+    return err_;
+}
+
+static NvError NvRmMemHandleFromId_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemHandleFromId_in *p_in;
+    NvRmMemHandleFromId_out *p_out;
+    NvRtObjRefHandle ref_hMem = 0;
+
+    p_in = (NvRmMemHandleFromId_in *)InBuffer;
+    p_out = (NvRmMemHandleFromId_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemHandleFromId_params, out) - OFFSET(NvRmMemHandleFromId_params, inout));
+
+    err_ = NvRtAllocObjRef(Ctx, &ref_hMem);
+    if (err_ != NvSuccess)
+    {
+        goto clean;
+    }
+
+    p_out->ret_ = NvRmMemHandleFromId( p_in->id, &p_out->hMem );
+
+    if ( p_out->ret_ == NvSuccess )
+    {
+        NvRtStoreObjRef(Ctx, ref_hMem, NvRtObjType_NvRm_NvRmMemHandle, p_out->hMem);
+        ref_hMem = 0;
+    }
+clean:
+    if (ref_hMem) NvRtDiscardObjRef(Ctx, ref_hMem);
+    return err_;
+}
+
+static NvError NvRmMemGetId_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetId_in *p_in;
+    NvRmMemGetId_out *p_out;
+
+    p_in = (NvRmMemGetId_in *)InBuffer;
+    p_out = (NvRmMemGetId_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetId_params, out) - OFFSET(NvRmMemGetId_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetId( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemGetHeapType_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetHeapType_in *p_in;
+    NvRmMemGetHeapType_out *p_out;
+
+    p_in = (NvRmMemGetHeapType_in *)InBuffer;
+    p_out = (NvRmMemGetHeapType_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetHeapType_params, out) - OFFSET(NvRmMemGetHeapType_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetHeapType( p_in->hMem, &p_out->BasePhysAddr );
+
+    return err_;
+}
+
+static NvError NvRmMemGetCacheLineSize_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetCacheLineSize_out *p_out;
+    p_out = (NvRmMemGetCacheLineSize_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetCacheLineSize_params, out) - OFFSET(NvRmMemGetCacheLineSize_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetCacheLineSize(  );
+
+    return err_;
+}
+
+static NvError NvRmMemGetAlignment_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetAlignment_in *p_in;
+    NvRmMemGetAlignment_out *p_out;
+
+    p_in = (NvRmMemGetAlignment_in *)InBuffer;
+    p_out = (NvRmMemGetAlignment_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetAlignment_params, out) - OFFSET(NvRmMemGetAlignment_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetAlignment( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemGetSize_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetSize_in *p_in;
+    NvRmMemGetSize_out *p_out;
+
+    p_in = (NvRmMemGetSize_in *)InBuffer;
+    p_out = (NvRmMemGetSize_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetSize_params, out) - OFFSET(NvRmMemGetSize_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetSize( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemMove_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemMove_in *p_in;
+
+    p_in = (NvRmMemMove_in *)InBuffer;
+
+
+    NvRmMemMove( p_in->hDstMem, p_in->DstOffset, p_in->hSrcMem, p_in->SrcOffset, p_in->Size );
+
+    return err_;
+}
+
+static NvError NvRmMemUnpinMult_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemUnpinMult_in *p_in;
+    NvRmMemHandle *hMems = NULL;
+
+    p_in = (NvRmMemUnpinMult_in *)InBuffer;
+
+    if( p_in->Count && p_in->hMems )
+    {
+        hMems = (NvRmMemHandle  *)NvOsAlloc( p_in->Count * sizeof( NvRmMemHandle  ) );
+        if( !hMems )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->hMems )
+        {
+            err_ = NvOsCopyIn( hMems, p_in->hMems, p_in->Count * sizeof( NvRmMemHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRmMemUnpinMult( hMems, p_in->Count );
+
+clean:
+    NvOsFree( hMems );
+    return err_;
+}
+
+static NvError NvRmMemUnpin_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemUnpin_in *p_in;
+
+    p_in = (NvRmMemUnpin_in *)InBuffer;
+
+
+    NvRmMemUnpin( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemGetAddress_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetAddress_in *p_in;
+    NvRmMemGetAddress_out *p_out;
+
+    p_in = (NvRmMemGetAddress_in *)InBuffer;
+    p_out = (NvRmMemGetAddress_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetAddress_params, out) - OFFSET(NvRmMemGetAddress_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetAddress( p_in->hMem, p_in->Offset );
+
+    return err_;
+}
+
+static NvError NvRmMemPinMult_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemPinMult_in *p_in;
+    NvRmMemHandle *hMems = NULL;
+    NvU32  *Addrs = NULL;
+
+    p_in = (NvRmMemPinMult_in *)InBuffer;
+
+    if( p_in->Count && p_in->hMems )
+    {
+        hMems = (NvRmMemHandle  *)NvOsAlloc( p_in->Count * sizeof( NvRmMemHandle  ) );
+        if( !hMems )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->hMems )
+        {
+            err_ = NvOsCopyIn( hMems, p_in->hMems, p_in->Count * sizeof( NvRmMemHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->Count && p_in->Addrs )
+    {
+        Addrs = (NvU32  *)NvOsAlloc( p_in->Count * sizeof( NvU32  ) );
+        if( !Addrs )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    NvRmMemPinMult( hMems, Addrs, p_in->Count );
+
+    if(p_in->Addrs && Addrs)
+    {
+        err_ = NvOsCopyOut( p_in->Addrs, Addrs, p_in->Count * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( hMems );
+    NvOsFree( Addrs );
+    return err_;
+}
+
+static NvError NvRmMemPin_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemPin_in *p_in;
+    NvRmMemPin_out *p_out;
+
+    p_in = (NvRmMemPin_in *)InBuffer;
+    p_out = (NvRmMemPin_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemPin_params, out) - OFFSET(NvRmMemPin_params, inout));
+
+
+    p_out->ret_ = NvRmMemPin( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemAlloc_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemAlloc_in *p_in;
+    NvRmMemAlloc_out *p_out;
+    NvRmHeap *Heaps = NULL;
+
+    p_in = (NvRmMemAlloc_in *)InBuffer;
+    p_out = (NvRmMemAlloc_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemAlloc_params, out) - OFFSET(NvRmMemAlloc_params, inout));
+
+    if( p_in->NumHeaps && p_in->Heaps )
+    {
+        Heaps = (NvRmHeap  *)NvOsAlloc( p_in->NumHeaps * sizeof( NvRmHeap  ) );
+        if( !Heaps )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Heaps )
+        {
+            err_ = NvOsCopyIn( Heaps, p_in->Heaps, p_in->NumHeaps * sizeof( NvRmHeap  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmMemAlloc( p_in->hMem, Heaps, p_in->NumHeaps, p_in->Alignment, p_in->Coherency );
+
+clean:
+    NvOsFree( Heaps );
+    return err_;
+}
+
+static NvError NvRmMemHandleFree_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemHandleFree_in *p_in;
+
+    p_in = (NvRmMemHandleFree_in *)InBuffer;
+
+    if (p_in->hMem != NULL) NvRtFreeObjRef(Ctx, NvRtObjType_NvRm_NvRmMemHandle, p_in->hMem);
+
+    NvRmMemHandleFree( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemHandlePreserveHandle_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemHandlePreserveHandle_in *p_in;
+    NvRmMemHandlePreserveHandle_out *p_out;
+
+    p_in = (NvRmMemHandlePreserveHandle_in *)InBuffer;
+    p_out = (NvRmMemHandlePreserveHandle_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemHandlePreserveHandle_params, out) - OFFSET(NvRmMemHandlePreserveHandle_params, inout));
+
+
+    p_out->ret_ = NvRmMemHandlePreserveHandle( p_in->hMem, &p_out->Key );
+
+    return err_;
+}
+
+static NvError NvRmMemHandleClaimPreservedHandle_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemHandleClaimPreservedHandle_in *p_in;
+    NvRmMemHandleClaimPreservedHandle_out *p_out;
+    NvRtObjRefHandle ref_phMem = 0;
+
+    p_in = (NvRmMemHandleClaimPreservedHandle_in *)InBuffer;
+    p_out = (NvRmMemHandleClaimPreservedHandle_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemHandleClaimPreservedHandle_params, out) - OFFSET(NvRmMemHandleClaimPreservedHandle_params, inout));
+
+    err_ = NvRtAllocObjRef(Ctx, &ref_phMem);
+    if (err_ != NvSuccess)
+    {
+        goto clean;
+    }
+
+    p_out->ret_ = NvRmMemHandleClaimPreservedHandle( p_in->hDevice, p_in->Key, &p_out->phMem );
+
+    if ( p_out->ret_ == NvSuccess )
+    {
+        NvRtStoreObjRef(Ctx, ref_phMem, NvRtObjType_NvRm_NvRmMemHandle, p_out->phMem);
+        ref_phMem = 0;
+    }
+clean:
+    if (ref_phMem) NvRtDiscardObjRef(Ctx, ref_phMem);
+    return err_;
+}
+
+static NvError NvRmMemHandleCreate_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemHandleCreate_in *p_in;
+    NvRmMemHandleCreate_out *p_out;
+    NvRtObjRefHandle ref_phMem = 0;
+
+    p_in = (NvRmMemHandleCreate_in *)InBuffer;
+    p_out = (NvRmMemHandleCreate_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemHandleCreate_params, out) - OFFSET(NvRmMemHandleCreate_params, inout));
+
+    err_ = NvRtAllocObjRef(Ctx, &ref_phMem);
+    if (err_ != NvSuccess)
+    {
+        goto clean;
+    }
+
+    p_out->ret_ = NvRmMemHandleCreate( p_in->hDevice, &p_out->phMem, p_in->Size );
+
+    if ( p_out->ret_ == NvSuccess )
+    {
+        NvRtStoreObjRef(Ctx, ref_phMem, NvRtObjType_NvRm_NvRmMemHandle, p_out->phMem);
+        ref_phMem = 0;
+    }
+clean:
+    if (ref_phMem) NvRtDiscardObjRef(Ctx, ref_phMem);
+    return err_;
+}
+
+NvError nvrm_memmgr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_memmgr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 17:
+        err_ = NvRmMemGetStat_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 16:
+        err_ = NvRmMemHandleFromId_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 15:
+        err_ = NvRmMemGetId_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 14:
+        err_ = NvRmMemGetHeapType_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 13:
+        err_ = NvRmMemGetCacheLineSize_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 12:
+        err_ = NvRmMemGetAlignment_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 11:
+        err_ = NvRmMemGetSize_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 10:
+        err_ = NvRmMemMove_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 9:
+        err_ = NvRmMemUnpinMult_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRmMemUnpin_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmMemGetAddress_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmMemPinMult_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmMemPin_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmMemAlloc_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmMemHandleFree_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmMemHandlePreserveHandle_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmMemHandleClaimPreservedHandle_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmMemHandleCreate_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_module_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_module_dispatch.c
new file mode 100644
index 000000000000..e4038b220cbf
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_module_dispatch.c
@@ -0,0 +1,966 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_module.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRegw08_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle rm;
+    NvRmModuleID aperture;
+    NvU32 offset;
+    NvU8 data;
+} NV_ALIGN(4) NvRegw08_in;
+
+typedef struct NvRegw08_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegw08_inout;
+
+typedef struct NvRegw08_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegw08_out;
+
+typedef struct NvRegw08_params_t
+{
+    NvRegw08_in in;
+    NvRegw08_inout inout;
+    NvRegw08_out out;
+} NvRegw08_params;
+
+typedef struct NvRegr08_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 offset;
+} NV_ALIGN(4) NvRegr08_in;
+
+typedef struct NvRegr08_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegr08_inout;
+
+typedef struct NvRegr08_out_t
+{
+    NvU8 ret_;
+} NV_ALIGN(4) NvRegr08_out;
+
+typedef struct NvRegr08_params_t
+{
+    NvRegr08_in in;
+    NvRegr08_inout inout;
+    NvRegr08_out out;
+} NvRegr08_params;
+
+typedef struct NvRegrb_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 num;
+    NvU32 offset;
+    NvU32  * values;
+} NV_ALIGN(4) NvRegrb_in;
+
+typedef struct NvRegrb_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegrb_inout;
+
+typedef struct NvRegrb_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegrb_out;
+
+typedef struct NvRegrb_params_t
+{
+    NvRegrb_in in;
+    NvRegrb_inout inout;
+    NvRegrb_out out;
+} NvRegrb_params;
+
+typedef struct NvRegwb_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 num;
+    NvU32 offset;
+    NvU32  * values;
+} NV_ALIGN(4) NvRegwb_in;
+
+typedef struct NvRegwb_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegwb_inout;
+
+typedef struct NvRegwb_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegwb_out;
+
+typedef struct NvRegwb_params_t
+{
+    NvRegwb_in in;
+    NvRegwb_inout inout;
+    NvRegwb_out out;
+} NvRegwb_params;
+
+typedef struct NvRegwm_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 num;
+    NvU32  * offsets;
+    NvU32  * values;
+} NV_ALIGN(4) NvRegwm_in;
+
+typedef struct NvRegwm_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegwm_inout;
+
+typedef struct NvRegwm_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegwm_out;
+
+typedef struct NvRegwm_params_t
+{
+    NvRegwm_in in;
+    NvRegwm_inout inout;
+    NvRegwm_out out;
+} NvRegwm_params;
+
+typedef struct NvRegrm_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 num;
+    NvU32  * offsets;
+    NvU32  * values;
+} NV_ALIGN(4) NvRegrm_in;
+
+typedef struct NvRegrm_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegrm_inout;
+
+typedef struct NvRegrm_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegrm_out;
+
+typedef struct NvRegrm_params_t
+{
+    NvRegrm_in in;
+    NvRegrm_inout inout;
+    NvRegrm_out out;
+} NvRegrm_params;
+
+typedef struct NvRegw_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 offset;
+    NvU32 data;
+} NV_ALIGN(4) NvRegw_in;
+
+typedef struct NvRegw_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegw_inout;
+
+typedef struct NvRegw_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegw_out;
+
+typedef struct NvRegw_params_t
+{
+    NvRegw_in in;
+    NvRegw_inout inout;
+    NvRegw_out out;
+} NvRegw_params;
+
+typedef struct NvRegr_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 offset;
+} NV_ALIGN(4) NvRegr_in;
+
+typedef struct NvRegr_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegr_inout;
+
+typedef struct NvRegr_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRegr_out;
+
+typedef struct NvRegr_params_t
+{
+    NvRegr_in in;
+    NvRegr_inout inout;
+    NvRegr_out out;
+} NvRegr_params;
+
+typedef struct NvRmGetRandomBytes_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 NumBytes;
+    void* pBytes;
+} NV_ALIGN(4) NvRmGetRandomBytes_in;
+
+typedef struct NvRmGetRandomBytes_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetRandomBytes_inout;
+
+typedef struct NvRmGetRandomBytes_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmGetRandomBytes_out;
+
+typedef struct NvRmGetRandomBytes_params_t
+{
+    NvRmGetRandomBytes_in in;
+    NvRmGetRandomBytes_inout inout;
+    NvRmGetRandomBytes_out out;
+} NvRmGetRandomBytes_params;
+
+typedef struct NvRmQueryChipUniqueId_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevHandle;
+    NvU32 IdSize;
+    void* pId;
+} NV_ALIGN(4) NvRmQueryChipUniqueId_in;
+
+typedef struct NvRmQueryChipUniqueId_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmQueryChipUniqueId_inout;
+
+typedef struct NvRmQueryChipUniqueId_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmQueryChipUniqueId_out;
+
+typedef struct NvRmQueryChipUniqueId_params_t
+{
+    NvRmQueryChipUniqueId_in in;
+    NvRmQueryChipUniqueId_inout inout;
+    NvRmQueryChipUniqueId_out out;
+} NvRmQueryChipUniqueId_params;
+
+typedef struct NvRmModuleGetCapabilities_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvRmModuleID Module;
+    NvRmModuleCapability  * pCaps;
+    NvU32 NumCaps;
+} NV_ALIGN(4) NvRmModuleGetCapabilities_in;
+
+typedef struct NvRmModuleGetCapabilities_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleGetCapabilities_inout;
+
+typedef struct NvRmModuleGetCapabilities_out_t
+{
+    NvError ret_;
+    void* Capability;
+} NV_ALIGN(4) NvRmModuleGetCapabilities_out;
+
+typedef struct NvRmModuleGetCapabilities_params_t
+{
+    NvRmModuleGetCapabilities_in in;
+    NvRmModuleGetCapabilities_inout inout;
+    NvRmModuleGetCapabilities_out out;
+} NvRmModuleGetCapabilities_params;
+
+typedef struct NvRmModuleResetWithHold_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID Module;
+    NvBool bHold;
+} NV_ALIGN(4) NvRmModuleResetWithHold_in;
+
+typedef struct NvRmModuleResetWithHold_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleResetWithHold_inout;
+
+typedef struct NvRmModuleResetWithHold_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleResetWithHold_out;
+
+typedef struct NvRmModuleResetWithHold_params_t
+{
+    NvRmModuleResetWithHold_in in;
+    NvRmModuleResetWithHold_inout inout;
+    NvRmModuleResetWithHold_out out;
+} NvRmModuleResetWithHold_params;
+
+typedef struct NvRmModuleReset_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID Module;
+} NV_ALIGN(4) NvRmModuleReset_in;
+
+typedef struct NvRmModuleReset_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleReset_inout;
+
+typedef struct NvRmModuleReset_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleReset_out;
+
+typedef struct NvRmModuleReset_params_t
+{
+    NvRmModuleReset_in in;
+    NvRmModuleReset_inout inout;
+    NvRmModuleReset_out out;
+} NvRmModuleReset_params;
+
+typedef struct NvRmModuleGetNumInstances_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID Module;
+} NV_ALIGN(4) NvRmModuleGetNumInstances_in;
+
+typedef struct NvRmModuleGetNumInstances_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleGetNumInstances_inout;
+
+typedef struct NvRmModuleGetNumInstances_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmModuleGetNumInstances_out;
+
+typedef struct NvRmModuleGetNumInstances_params_t
+{
+    NvRmModuleGetNumInstances_in in;
+    NvRmModuleGetNumInstances_inout inout;
+    NvRmModuleGetNumInstances_out out;
+} NvRmModuleGetNumInstances_params;
+
+typedef struct NvRmModuleGetBaseAddress_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID Module;
+} NV_ALIGN(4) NvRmModuleGetBaseAddress_in;
+
+typedef struct NvRmModuleGetBaseAddress_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleGetBaseAddress_inout;
+
+typedef struct NvRmModuleGetBaseAddress_out_t
+{
+    NvRmPhysAddr pBaseAddress;
+    NvU32 pSize;
+} NV_ALIGN(4) NvRmModuleGetBaseAddress_out;
+
+typedef struct NvRmModuleGetBaseAddress_params_t
+{
+    NvRmModuleGetBaseAddress_in in;
+    NvRmModuleGetBaseAddress_inout inout;
+    NvRmModuleGetBaseAddress_out out;
+} NvRmModuleGetBaseAddress_params;
+
+typedef struct NvRmModuleGetModuleInfo_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmModuleID module;
+    NvRmModuleInfo  * pModuleInfo;
+} NV_ALIGN(4) NvRmModuleGetModuleInfo_in;
+
+typedef struct NvRmModuleGetModuleInfo_inout_t
+{
+    NvU32 pNum;
+} NV_ALIGN(4) NvRmModuleGetModuleInfo_inout;
+
+typedef struct NvRmModuleGetModuleInfo_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmModuleGetModuleInfo_out;
+
+typedef struct NvRmModuleGetModuleInfo_params_t
+{
+    NvRmModuleGetModuleInfo_in in;
+    NvRmModuleGetModuleInfo_inout inout;
+    NvRmModuleGetModuleInfo_out out;
+} NvRmModuleGetModuleInfo_params;
+
+static NvError NvRegw08_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRegw08_in *p_in;
+
+    p_in = (NvRegw08_in *)InBuffer;
+
+
+    NvRegw08( p_in->rm, p_in->aperture, p_in->offset, p_in->data );
+
+    return err_;
+}
+
+static NvError NvRegr08_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRegr08_in *p_in;
+    NvRegr08_out *p_out;
+
+    p_in = (NvRegr08_in *)InBuffer;
+    p_out = (NvRegr08_out *)((NvU8 *)OutBuffer + OFFSET(NvRegr08_params, out) - OFFSET(NvRegr08_params, inout));
+
+
+    p_out->ret_ = NvRegr08( p_in->hDeviceHandle, p_in->aperture, p_in->offset );
+
+    return err_;
+}
+
+static NvError NvRegrb_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRegrb_in *p_in;
+    NvU32  *values = NULL;
+
+    p_in = (NvRegrb_in *)InBuffer;
+
+    if( p_in->num && p_in->values )
+    {
+        values = (NvU32  *)NvOsAlloc( p_in->num * sizeof( NvU32  ) );
+        if( !values )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    NvRegrb( p_in->hRmDeviceHandle, p_in->aperture, p_in->num, p_in->offset, values );
+
+    if(p_in->values && values)
+    {
+        err_ = NvOsCopyOut( p_in->values, values, p_in->num * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( values );
+    return err_;
+}
+
+static NvError NvRegwb_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRegwb_in *p_in;
+    NvU32  *values = NULL;
+
+    p_in = (NvRegwb_in *)InBuffer;
+
+    if( p_in->num && p_in->values )
+    {
+        values = (NvU32  *)NvOsAlloc( p_in->num * sizeof( NvU32  ) );
+        if( !values )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->values )
+        {
+            err_ = NvOsCopyIn( values, p_in->values, p_in->num * sizeof( NvU32  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRegwb( p_in->hRmDeviceHandle, p_in->aperture, p_in->num, p_in->offset, values );
+
+clean:
+    NvOsFree( values );
+    return err_;
+}
+
+static NvError NvRegwm_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRegwm_in *p_in;
+    NvU32  *offsets = NULL;
+    NvU32  *values = NULL;
+
+    p_in = (NvRegwm_in *)InBuffer;
+
+    if( p_in->num && p_in->offsets )
+    {
+        offsets = (NvU32  *)NvOsAlloc( p_in->num * sizeof( NvU32  ) );
+        if( !offsets )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->offsets )
+        {
+            err_ = NvOsCopyIn( offsets, p_in->offsets, p_in->num * sizeof( NvU32  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->num && p_in->values )
+    {
+        values = (NvU32  *)NvOsAlloc( p_in->num * sizeof( NvU32  ) );
+        if( !values )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->values )
+        {
+            err_ = NvOsCopyIn( values, p_in->values, p_in->num * sizeof( NvU32  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRegwm( p_in->hRmDeviceHandle, p_in->aperture, p_in->num, offsets, values );
+
+clean:
+    NvOsFree( offsets );
+    NvOsFree( values );
+    return err_;
+}
+
+static NvError NvRegrm_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRegrm_in *p_in;
+    NvU32  *offsets = NULL;
+    NvU32  *values = NULL;
+
+    p_in = (NvRegrm_in *)InBuffer;
+
+    if( p_in->num && p_in->offsets )
+    {
+        offsets = (NvU32  *)NvOsAlloc( p_in->num * sizeof( NvU32  ) );
+        if( !offsets )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->offsets )
+        {
+            err_ = NvOsCopyIn( offsets, p_in->offsets, p_in->num * sizeof( NvU32  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->num && p_in->values )
+    {
+        values = (NvU32  *)NvOsAlloc( p_in->num * sizeof( NvU32  ) );
+        if( !values )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    NvRegrm( p_in->hRmDeviceHandle, p_in->aperture, p_in->num, offsets, values );
+
+    if(p_in->values && values)
+    {
+        err_ = NvOsCopyOut( p_in->values, values, p_in->num * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( offsets );
+    NvOsFree( values );
+    return err_;
+}
+
+static NvError NvRegw_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRegw_in *p_in;
+
+    p_in = (NvRegw_in *)InBuffer;
+
+
+    NvRegw( p_in->hDeviceHandle, p_in->aperture, p_in->offset, p_in->data );
+
+    return err_;
+}
+
+static NvError NvRegr_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRegr_in *p_in;
+    NvRegr_out *p_out;
+
+    p_in = (NvRegr_in *)InBuffer;
+    p_out = (NvRegr_out *)((NvU8 *)OutBuffer + OFFSET(NvRegr_params, out) - OFFSET(NvRegr_params, inout));
+
+
+    p_out->ret_ = NvRegr( p_in->hDeviceHandle, p_in->aperture, p_in->offset );
+
+    return err_;
+}
+
+static NvError NvRmGetRandomBytes_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetRandomBytes_in *p_in;
+    NvRmGetRandomBytes_out *p_out;
+    void*  pBytes = NULL;
+
+    p_in = (NvRmGetRandomBytes_in *)InBuffer;
+    p_out = (NvRmGetRandomBytes_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetRandomBytes_params, out) - OFFSET(NvRmGetRandomBytes_params, inout));
+
+    if( p_in->NumBytes && p_in->pBytes )
+    {
+        pBytes = (void*  )NvOsAlloc( p_in->NumBytes );
+        if( !pBytes )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmGetRandomBytes( p_in->hRmDeviceHandle, p_in->NumBytes, pBytes );
+
+    if(p_in->pBytes && pBytes)
+    {
+        err_ = NvOsCopyOut( p_in->pBytes, pBytes, p_in->NumBytes );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pBytes );
+    return err_;
+}
+
+static NvError NvRmQueryChipUniqueId_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmQueryChipUniqueId_in *p_in;
+    NvRmQueryChipUniqueId_out *p_out;
+    void*  pId = NULL;
+
+    p_in = (NvRmQueryChipUniqueId_in *)InBuffer;
+    p_out = (NvRmQueryChipUniqueId_out *)((NvU8 *)OutBuffer + OFFSET(NvRmQueryChipUniqueId_params, out) - OFFSET(NvRmQueryChipUniqueId_params, inout));
+
+    if( p_in->IdSize && p_in->pId )
+    {
+        pId = (void*  )NvOsAlloc( p_in->IdSize );
+        if( !pId )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmQueryChipUniqueId( p_in->hDevHandle, p_in->IdSize, pId );
+
+    if(p_in->pId && pId)
+    {
+        err_ = NvOsCopyOut( p_in->pId, pId, p_in->IdSize );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pId );
+    return err_;
+}
+
+static NvError NvRmModuleGetCapabilities_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmModuleGetCapabilities_in *p_in;
+    NvRmModuleGetCapabilities_out *p_out;
+    NvRmModuleCapability *pCaps = NULL;
+
+    p_in = (NvRmModuleGetCapabilities_in *)InBuffer;
+    p_out = (NvRmModuleGetCapabilities_out *)((NvU8 *)OutBuffer + OFFSET(NvRmModuleGetCapabilities_params, out) - OFFSET(NvRmModuleGetCapabilities_params, inout));
+
+    if( p_in->NumCaps && p_in->pCaps )
+    {
+        pCaps = (NvRmModuleCapability  *)NvOsAlloc( p_in->NumCaps * sizeof( NvRmModuleCapability  ) );
+        if( !pCaps )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pCaps )
+        {
+            err_ = NvOsCopyIn( pCaps, p_in->pCaps, p_in->NumCaps * sizeof( NvRmModuleCapability  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmModuleGetCapabilities( p_in->hDeviceHandle, p_in->Module, pCaps, p_in->NumCaps, &p_out->Capability );
+
+clean:
+    NvOsFree( pCaps );
+    return err_;
+}
+
+static NvError NvRmModuleResetWithHold_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmModuleResetWithHold_in *p_in;
+
+    p_in = (NvRmModuleResetWithHold_in *)InBuffer;
+
+
+    NvRmModuleResetWithHold( p_in->hRmDeviceHandle, p_in->Module, p_in->bHold );
+
+    return err_;
+}
+
+static NvError NvRmModuleReset_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmModuleReset_in *p_in;
+
+    p_in = (NvRmModuleReset_in *)InBuffer;
+
+
+    NvRmModuleReset( p_in->hRmDeviceHandle, p_in->Module );
+
+    return err_;
+}
+
+static NvError NvRmModuleGetNumInstances_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmModuleGetNumInstances_in *p_in;
+    NvRmModuleGetNumInstances_out *p_out;
+
+    p_in = (NvRmModuleGetNumInstances_in *)InBuffer;
+    p_out = (NvRmModuleGetNumInstances_out *)((NvU8 *)OutBuffer + OFFSET(NvRmModuleGetNumInstances_params, out) - OFFSET(NvRmModuleGetNumInstances_params, inout));
+
+
+    p_out->ret_ = NvRmModuleGetNumInstances( p_in->hRmDeviceHandle, p_in->Module );
+
+    return err_;
+}
+
+static NvError NvRmModuleGetBaseAddress_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmModuleGetBaseAddress_in *p_in;
+    NvRmModuleGetBaseAddress_out *p_out;
+
+    p_in = (NvRmModuleGetBaseAddress_in *)InBuffer;
+    p_out = (NvRmModuleGetBaseAddress_out *)((NvU8 *)OutBuffer + OFFSET(NvRmModuleGetBaseAddress_params, out) - OFFSET(NvRmModuleGetBaseAddress_params, inout));
+
+
+    NvRmModuleGetBaseAddress( p_in->hRmDeviceHandle, p_in->Module, &p_out->pBaseAddress, &p_out->pSize );
+
+    return err_;
+}
+
+static NvError NvRmModuleGetModuleInfo_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmModuleGetModuleInfo_in *p_in;
+    NvRmModuleGetModuleInfo_inout *p_inout;
+    NvRmModuleGetModuleInfo_out *p_out;
+    NvRmModuleGetModuleInfo_inout inout;
+    NvRmModuleInfo *pModuleInfo = NULL;
+
+    p_in = (NvRmModuleGetModuleInfo_in *)InBuffer;
+    p_inout = (NvRmModuleGetModuleInfo_inout *)((NvU8 *)InBuffer + OFFSET(NvRmModuleGetModuleInfo_params, inout));
+    p_out = (NvRmModuleGetModuleInfo_out *)((NvU8 *)OutBuffer + OFFSET(NvRmModuleGetModuleInfo_params, out) - OFFSET(NvRmModuleGetModuleInfo_params, inout));
+
+    (void)inout;
+    inout.pNum = p_inout->pNum;
+    if( p_inout->pNum && p_in->pModuleInfo )
+    {
+        pModuleInfo = (NvRmModuleInfo  *)NvOsAlloc( p_inout->pNum * sizeof( NvRmModuleInfo  ) );
+        if( !pModuleInfo )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmModuleGetModuleInfo( p_in->hDevice, p_in->module, &inout.pNum, pModuleInfo );
+
+
+    p_inout = (NvRmModuleGetModuleInfo_inout *)OutBuffer;
+    p_inout->pNum = inout.pNum;
+    if(p_in->pModuleInfo && pModuleInfo)
+    {
+        err_ = NvOsCopyOut( p_in->pModuleInfo, pModuleInfo, p_inout->pNum * sizeof( NvRmModuleInfo  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pModuleInfo );
+    return err_;
+}
+
+NvError nvrm_module_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_module_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 15:
+        err_ = NvRegw08_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 14:
+        err_ = NvRegr08_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 13:
+        err_ = NvRegrb_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 12:
+        err_ = NvRegwb_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 11:
+        err_ = NvRegwm_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 10:
+        err_ = NvRegrm_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 9:
+        err_ = NvRegw_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRegr_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmGetRandomBytes_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmQueryChipUniqueId_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmModuleGetCapabilities_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmModuleResetWithHold_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmModuleReset_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmModuleGetNumInstances_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmModuleGetBaseAddress_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmModuleGetModuleInfo_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_owr_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_owr_dispatch.c
new file mode 100644
index 000000000000..57f9b7b703e8
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_owr_dispatch.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_owr.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmOwrTransaction_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmOwrHandle hOwr;
+    NvU32 OwrPinMap;
+    NvU8  * Data;
+    NvU32 DataLen;
+    NvRmOwrTransactionInfo  * Transaction;
+    NvU32 NumOfTransactions;
+} NV_ALIGN(4) NvRmOwrTransaction_in;
+
+typedef struct NvRmOwrTransaction_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOwrTransaction_inout;
+
+typedef struct NvRmOwrTransaction_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmOwrTransaction_out;
+
+typedef struct NvRmOwrTransaction_params_t
+{
+    NvRmOwrTransaction_in in;
+    NvRmOwrTransaction_inout inout;
+    NvRmOwrTransaction_out out;
+} NvRmOwrTransaction_params;
+
+typedef struct NvRmOwrClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmOwrHandle hOwr;
+} NV_ALIGN(4) NvRmOwrClose_in;
+
+typedef struct NvRmOwrClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOwrClose_inout;
+
+typedef struct NvRmOwrClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOwrClose_out;
+
+typedef struct NvRmOwrClose_params_t
+{
+    NvRmOwrClose_in in;
+    NvRmOwrClose_inout inout;
+    NvRmOwrClose_out out;
+} NvRmOwrClose_params;
+
+typedef struct NvRmOwrOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 instance;
+} NV_ALIGN(4) NvRmOwrOpen_in;
+
+typedef struct NvRmOwrOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOwrOpen_inout;
+
+typedef struct NvRmOwrOpen_out_t
+{
+    NvError ret_;
+    NvRmOwrHandle hOwr;
+} NV_ALIGN(4) NvRmOwrOpen_out;
+
+typedef struct NvRmOwrOpen_params_t
+{
+    NvRmOwrOpen_in in;
+    NvRmOwrOpen_inout inout;
+    NvRmOwrOpen_out out;
+} NvRmOwrOpen_params;
+
+static NvError NvRmOwrTransaction_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmOwrTransaction_in *p_in;
+    NvRmOwrTransaction_out *p_out;
+    NvU8  *Data = NULL;
+    NvRmOwrTransactionInfo *Transaction = NULL;
+
+    p_in = (NvRmOwrTransaction_in *)InBuffer;
+    p_out = (NvRmOwrTransaction_out *)((NvU8 *)OutBuffer + OFFSET(NvRmOwrTransaction_params, out) - OFFSET(NvRmOwrTransaction_params, inout));
+
+    if( p_in->DataLen && p_in->Data )
+    {
+        Data = (NvU8  *)NvOsAlloc( p_in->DataLen * sizeof( NvU8  ) );
+        if( !Data )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Data )
+        {
+            err_ = NvOsCopyIn( Data, p_in->Data, p_in->DataLen * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->NumOfTransactions && p_in->Transaction )
+    {
+        Transaction = (NvRmOwrTransactionInfo  *)NvOsAlloc( p_in->NumOfTransactions * sizeof( NvRmOwrTransactionInfo  ) );
+        if( !Transaction )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Transaction )
+        {
+            err_ = NvOsCopyIn( Transaction, p_in->Transaction, p_in->NumOfTransactions * sizeof( NvRmOwrTransactionInfo  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmOwrTransaction( p_in->hOwr, p_in->OwrPinMap, Data, p_in->DataLen, Transaction, p_in->NumOfTransactions );
+
+    if(p_in->Data && Data)
+    {
+        err_ = NvOsCopyOut( p_in->Data, Data, p_in->DataLen * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( Data );
+    NvOsFree( Transaction );
+    return err_;
+}
+
+static NvError NvRmOwrClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmOwrClose_in *p_in;
+
+    p_in = (NvRmOwrClose_in *)InBuffer;
+
+
+    NvRmOwrClose( p_in->hOwr );
+
+    return err_;
+}
+
+static NvError NvRmOwrOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmOwrOpen_in *p_in;
+    NvRmOwrOpen_out *p_out;
+
+    p_in = (NvRmOwrOpen_in *)InBuffer;
+    p_out = (NvRmOwrOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmOwrOpen_params, out) - OFFSET(NvRmOwrOpen_params, inout));
+
+
+    p_out->ret_ = NvRmOwrOpen( p_in->hDevice, p_in->instance, &p_out->hOwr );
+
+    return err_;
+}
+
+NvError nvrm_owr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_owr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 2:
+        err_ = NvRmOwrTransaction_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmOwrClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmOwrOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_pinmux_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_pinmux_dispatch.c
new file mode 100644
index 000000000000..4064ca6e0029
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_pinmux_dispatch.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_pinmux.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmGetStraps_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmStrapGroup StrapGroup;
+} NV_ALIGN(4) NvRmGetStraps_in;
+
+typedef struct NvRmGetStraps_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetStraps_inout;
+
+typedef struct NvRmGetStraps_out_t
+{
+    NvError ret_;
+    NvU32 pStrapValue;
+} NV_ALIGN(4) NvRmGetStraps_out;
+
+typedef struct NvRmGetStraps_params_t
+{
+    NvRmGetStraps_in in;
+    NvRmGetStraps_inout inout;
+    NvRmGetStraps_out out;
+} NvRmGetStraps_params;
+
+typedef struct NvRmGetModuleInterfaceCapabilities_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRm;
+    NvRmModuleID ModuleId;
+    NvU32 CapStructSize;
+    void* pCaps;
+} NV_ALIGN(4) NvRmGetModuleInterfaceCapabilities_in;
+
+typedef struct NvRmGetModuleInterfaceCapabilities_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetModuleInterfaceCapabilities_inout;
+
+typedef struct NvRmGetModuleInterfaceCapabilities_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmGetModuleInterfaceCapabilities_out;
+
+typedef struct NvRmGetModuleInterfaceCapabilities_params_t
+{
+    NvRmGetModuleInterfaceCapabilities_in in;
+    NvRmGetModuleInterfaceCapabilities_inout inout;
+    NvRmGetModuleInterfaceCapabilities_out out;
+} NvRmGetModuleInterfaceCapabilities_params;
+
+typedef struct NvRmExternalClockConfig_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 IoModule;
+    NvU32 Instance;
+    NvU32 Config;
+    NvBool EnableTristate;
+} NV_ALIGN(4) NvRmExternalClockConfig_in;
+
+typedef struct NvRmExternalClockConfig_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmExternalClockConfig_inout;
+
+typedef struct NvRmExternalClockConfig_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmExternalClockConfig_out;
+
+typedef struct NvRmExternalClockConfig_params_t
+{
+    NvRmExternalClockConfig_in in;
+    NvRmExternalClockConfig_inout inout;
+    NvRmExternalClockConfig_out out;
+} NvRmExternalClockConfig_params;
+
+typedef struct NvRmSetOdmModuleTristate_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 OdmModule;
+    NvU32 OdmInstance;
+    NvBool EnableTristate;
+} NV_ALIGN(4) NvRmSetOdmModuleTristate_in;
+
+typedef struct NvRmSetOdmModuleTristate_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSetOdmModuleTristate_inout;
+
+typedef struct NvRmSetOdmModuleTristate_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmSetOdmModuleTristate_out;
+
+typedef struct NvRmSetOdmModuleTristate_params_t
+{
+    NvRmSetOdmModuleTristate_in in;
+    NvRmSetOdmModuleTristate_inout inout;
+    NvRmSetOdmModuleTristate_out out;
+} NvRmSetOdmModuleTristate_params;
+
+typedef struct NvRmSetModuleTristate_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmModuleID RmModule;
+    NvBool EnableTristate;
+} NV_ALIGN(4) NvRmSetModuleTristate_in;
+
+typedef struct NvRmSetModuleTristate_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSetModuleTristate_inout;
+
+typedef struct NvRmSetModuleTristate_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmSetModuleTristate_out;
+
+typedef struct NvRmSetModuleTristate_params_t
+{
+    NvRmSetModuleTristate_in in;
+    NvRmSetModuleTristate_inout inout;
+    NvRmSetModuleTristate_out out;
+} NvRmSetModuleTristate_params;
+
+static NvError NvRmGetStraps_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetStraps_in *p_in;
+    NvRmGetStraps_out *p_out;
+
+    p_in = (NvRmGetStraps_in *)InBuffer;
+    p_out = (NvRmGetStraps_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetStraps_params, out) - OFFSET(NvRmGetStraps_params, inout));
+
+
+    p_out->ret_ = NvRmGetStraps( p_in->hDevice, p_in->StrapGroup, &p_out->pStrapValue );
+
+    return err_;
+}
+
+static NvError NvRmGetModuleInterfaceCapabilities_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetModuleInterfaceCapabilities_in *p_in;
+    NvRmGetModuleInterfaceCapabilities_out *p_out;
+    void*  pCaps = NULL;
+
+    p_in = (NvRmGetModuleInterfaceCapabilities_in *)InBuffer;
+    p_out = (NvRmGetModuleInterfaceCapabilities_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetModuleInterfaceCapabilities_params, out) - OFFSET(NvRmGetModuleInterfaceCapabilities_params, inout));
+
+    if( p_in->CapStructSize && p_in->pCaps )
+    {
+        pCaps = (void*  )NvOsAlloc( p_in->CapStructSize );
+        if( !pCaps )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmGetModuleInterfaceCapabilities( p_in->hRm, p_in->ModuleId, p_in->CapStructSize, pCaps );
+
+    if(p_in->pCaps && pCaps)
+    {
+        err_ = NvOsCopyOut( p_in->pCaps, pCaps, p_in->CapStructSize );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pCaps );
+    return err_;
+}
+
+static NvError NvRmExternalClockConfig_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmExternalClockConfig_in *p_in;
+    NvRmExternalClockConfig_out *p_out;
+
+    p_in = (NvRmExternalClockConfig_in *)InBuffer;
+    p_out = (NvRmExternalClockConfig_out *)((NvU8 *)OutBuffer + OFFSET(NvRmExternalClockConfig_params, out) - OFFSET(NvRmExternalClockConfig_params, inout));
+
+
+    p_out->ret_ = NvRmExternalClockConfig( p_in->hDevice, p_in->IoModule, p_in->Instance, p_in->Config, p_in->EnableTristate );
+
+    return err_;
+}
+
+static NvError NvRmSetOdmModuleTristate_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSetOdmModuleTristate_in *p_in;
+    NvRmSetOdmModuleTristate_out *p_out;
+
+    p_in = (NvRmSetOdmModuleTristate_in *)InBuffer;
+    p_out = (NvRmSetOdmModuleTristate_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSetOdmModuleTristate_params, out) - OFFSET(NvRmSetOdmModuleTristate_params, inout));
+
+
+    p_out->ret_ = NvRmSetOdmModuleTristate( p_in->hDevice, p_in->OdmModule, p_in->OdmInstance, p_in->EnableTristate );
+
+    return err_;
+}
+
+static NvError NvRmSetModuleTristate_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSetModuleTristate_in *p_in;
+    NvRmSetModuleTristate_out *p_out;
+
+    p_in = (NvRmSetModuleTristate_in *)InBuffer;
+    p_out = (NvRmSetModuleTristate_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSetModuleTristate_params, out) - OFFSET(NvRmSetModuleTristate_params, inout));
+
+
+    p_out->ret_ = NvRmSetModuleTristate( p_in->hDevice, p_in->RmModule, p_in->EnableTristate );
+
+    return err_;
+}
+
+NvError nvrm_pinmux_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pinmux_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 4:
+        err_ = NvRmGetStraps_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmGetModuleInterfaceCapabilities_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmExternalClockConfig_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmSetOdmModuleTristate_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmSetModuleTristate_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_pmu_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_pmu_dispatch.c
new file mode 100644
index 000000000000..593d6e256bd7
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_pmu_dispatch.c
@@ -0,0 +1,617 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_pmu.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmPmuIsRtcInitialized_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmPmuIsRtcInitialized_in;
+
+typedef struct NvRmPmuIsRtcInitialized_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuIsRtcInitialized_inout;
+
+typedef struct NvRmPmuIsRtcInitialized_out_t
+{
+    NvBool ret_;
+} NV_ALIGN(4) NvRmPmuIsRtcInitialized_out;
+
+typedef struct NvRmPmuIsRtcInitialized_params_t
+{
+    NvRmPmuIsRtcInitialized_in in;
+    NvRmPmuIsRtcInitialized_inout inout;
+    NvRmPmuIsRtcInitialized_out out;
+} NvRmPmuIsRtcInitialized_params;
+
+typedef struct NvRmPmuWriteRtc_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvU32 Count;
+} NV_ALIGN(4) NvRmPmuWriteRtc_in;
+
+typedef struct NvRmPmuWriteRtc_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuWriteRtc_inout;
+
+typedef struct NvRmPmuWriteRtc_out_t
+{
+    NvBool ret_;
+} NV_ALIGN(4) NvRmPmuWriteRtc_out;
+
+typedef struct NvRmPmuWriteRtc_params_t
+{
+    NvRmPmuWriteRtc_in in;
+    NvRmPmuWriteRtc_inout inout;
+    NvRmPmuWriteRtc_out out;
+} NvRmPmuWriteRtc_params;
+
+typedef struct NvRmPmuReadRtc_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmPmuReadRtc_in;
+
+typedef struct NvRmPmuReadRtc_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuReadRtc_inout;
+
+typedef struct NvRmPmuReadRtc_out_t
+{
+    NvBool ret_;
+    NvU32 pCount;
+} NV_ALIGN(4) NvRmPmuReadRtc_out;
+
+typedef struct NvRmPmuReadRtc_params_t
+{
+    NvRmPmuReadRtc_in in;
+    NvRmPmuReadRtc_inout inout;
+    NvRmPmuReadRtc_out out;
+} NvRmPmuReadRtc_params;
+
+typedef struct NvRmPmuGetBatteryChemistry_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmPmuBatteryInstance batteryInst;
+} NV_ALIGN(4) NvRmPmuGetBatteryChemistry_in;
+
+typedef struct NvRmPmuGetBatteryChemistry_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetBatteryChemistry_inout;
+
+typedef struct NvRmPmuGetBatteryChemistry_out_t
+{
+    NvRmPmuBatteryChemistry pChemistry;
+} NV_ALIGN(4) NvRmPmuGetBatteryChemistry_out;
+
+typedef struct NvRmPmuGetBatteryChemistry_params_t
+{
+    NvRmPmuGetBatteryChemistry_in in;
+    NvRmPmuGetBatteryChemistry_inout inout;
+    NvRmPmuGetBatteryChemistry_out out;
+} NvRmPmuGetBatteryChemistry_params;
+
+typedef struct NvRmPmuGetBatteryFullLifeTime_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmPmuBatteryInstance batteryInst;
+} NV_ALIGN(4) NvRmPmuGetBatteryFullLifeTime_in;
+
+typedef struct NvRmPmuGetBatteryFullLifeTime_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetBatteryFullLifeTime_inout;
+
+typedef struct NvRmPmuGetBatteryFullLifeTime_out_t
+{
+    NvU32 pLifeTime;
+} NV_ALIGN(4) NvRmPmuGetBatteryFullLifeTime_out;
+
+typedef struct NvRmPmuGetBatteryFullLifeTime_params_t
+{
+    NvRmPmuGetBatteryFullLifeTime_in in;
+    NvRmPmuGetBatteryFullLifeTime_inout inout;
+    NvRmPmuGetBatteryFullLifeTime_out out;
+} NvRmPmuGetBatteryFullLifeTime_params;
+
+typedef struct NvRmPmuGetBatteryData_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmPmuBatteryInstance batteryInst;
+} NV_ALIGN(4) NvRmPmuGetBatteryData_in;
+
+typedef struct NvRmPmuGetBatteryData_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetBatteryData_inout;
+
+typedef struct NvRmPmuGetBatteryData_out_t
+{
+    NvBool ret_;
+    NvRmPmuBatteryData pData;
+} NV_ALIGN(4) NvRmPmuGetBatteryData_out;
+
+typedef struct NvRmPmuGetBatteryData_params_t
+{
+    NvRmPmuGetBatteryData_in in;
+    NvRmPmuGetBatteryData_inout inout;
+    NvRmPmuGetBatteryData_out out;
+} NvRmPmuGetBatteryData_params;
+
+typedef struct NvRmPmuGetBatteryStatus_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmPmuBatteryInstance batteryInst;
+} NV_ALIGN(4) NvRmPmuGetBatteryStatus_in;
+
+typedef struct NvRmPmuGetBatteryStatus_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetBatteryStatus_inout;
+
+typedef struct NvRmPmuGetBatteryStatus_out_t
+{
+    NvBool ret_;
+    NvU8 pStatus;
+} NV_ALIGN(4) NvRmPmuGetBatteryStatus_out;
+
+typedef struct NvRmPmuGetBatteryStatus_params_t
+{
+    NvRmPmuGetBatteryStatus_in in;
+    NvRmPmuGetBatteryStatus_inout inout;
+    NvRmPmuGetBatteryStatus_out out;
+} NvRmPmuGetBatteryStatus_params;
+
+typedef struct NvRmPmuGetAcLineStatus_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmPmuGetAcLineStatus_in;
+
+typedef struct NvRmPmuGetAcLineStatus_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetAcLineStatus_inout;
+
+typedef struct NvRmPmuGetAcLineStatus_out_t
+{
+    NvBool ret_;
+    NvRmPmuAcLineStatus pStatus;
+} NV_ALIGN(4) NvRmPmuGetAcLineStatus_out;
+
+typedef struct NvRmPmuGetAcLineStatus_params_t
+{
+    NvRmPmuGetAcLineStatus_in in;
+    NvRmPmuGetAcLineStatus_inout inout;
+    NvRmPmuGetAcLineStatus_out out;
+} NvRmPmuGetAcLineStatus_params;
+
+typedef struct NvRmPmuSetChargingCurrentLimit_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmPmuChargingPath ChargingPath;
+    NvU32 ChargingCurrentLimitMa;
+    NvU32 ChargerType;
+} NV_ALIGN(4) NvRmPmuSetChargingCurrentLimit_in;
+
+typedef struct NvRmPmuSetChargingCurrentLimit_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuSetChargingCurrentLimit_inout;
+
+typedef struct NvRmPmuSetChargingCurrentLimit_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuSetChargingCurrentLimit_out;
+
+typedef struct NvRmPmuSetChargingCurrentLimit_params_t
+{
+    NvRmPmuSetChargingCurrentLimit_in in;
+    NvRmPmuSetChargingCurrentLimit_inout inout;
+    NvRmPmuSetChargingCurrentLimit_out out;
+} NvRmPmuSetChargingCurrentLimit_params;
+
+typedef struct NvRmPmuSetSocRailPowerState_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 vddId;
+    NvBool Enable;
+} NV_ALIGN(4) NvRmPmuSetSocRailPowerState_in;
+
+typedef struct NvRmPmuSetSocRailPowerState_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuSetSocRailPowerState_inout;
+
+typedef struct NvRmPmuSetSocRailPowerState_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuSetSocRailPowerState_out;
+
+typedef struct NvRmPmuSetSocRailPowerState_params_t
+{
+    NvRmPmuSetSocRailPowerState_in in;
+    NvRmPmuSetSocRailPowerState_inout inout;
+    NvRmPmuSetSocRailPowerState_out out;
+} NvRmPmuSetSocRailPowerState_params;
+
+typedef struct NvRmPmuSetVoltage_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 vddId;
+    NvU32 MilliVolts;
+} NV_ALIGN(4) NvRmPmuSetVoltage_in;
+
+typedef struct NvRmPmuSetVoltage_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuSetVoltage_inout;
+
+typedef struct NvRmPmuSetVoltage_out_t
+{
+    NvU32 pSettleMicroSeconds;
+} NV_ALIGN(4) NvRmPmuSetVoltage_out;
+
+typedef struct NvRmPmuSetVoltage_params_t
+{
+    NvRmPmuSetVoltage_in in;
+    NvRmPmuSetVoltage_inout inout;
+    NvRmPmuSetVoltage_out out;
+} NvRmPmuSetVoltage_params;
+
+typedef struct NvRmPmuGetVoltage_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 vddId;
+} NV_ALIGN(4) NvRmPmuGetVoltage_in;
+
+typedef struct NvRmPmuGetVoltage_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetVoltage_inout;
+
+typedef struct NvRmPmuGetVoltage_out_t
+{
+    NvU32 pMilliVolts;
+} NV_ALIGN(4) NvRmPmuGetVoltage_out;
+
+typedef struct NvRmPmuGetVoltage_params_t
+{
+    NvRmPmuGetVoltage_in in;
+    NvRmPmuGetVoltage_inout inout;
+    NvRmPmuGetVoltage_out out;
+} NvRmPmuGetVoltage_params;
+
+typedef struct NvRmPmuGetCapabilities_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 vddId;
+} NV_ALIGN(4) NvRmPmuGetCapabilities_in;
+
+typedef struct NvRmPmuGetCapabilities_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetCapabilities_inout;
+
+typedef struct NvRmPmuGetCapabilities_out_t
+{
+    NvRmPmuVddRailCapabilities pCapabilities;
+} NV_ALIGN(4) NvRmPmuGetCapabilities_out;
+
+typedef struct NvRmPmuGetCapabilities_params_t
+{
+    NvRmPmuGetCapabilities_in in;
+    NvRmPmuGetCapabilities_inout inout;
+    NvRmPmuGetCapabilities_out out;
+} NvRmPmuGetCapabilities_params;
+
+static NvError NvRmPmuIsRtcInitialized_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuIsRtcInitialized_in *p_in;
+    NvRmPmuIsRtcInitialized_out *p_out;
+
+    p_in = (NvRmPmuIsRtcInitialized_in *)InBuffer;
+    p_out = (NvRmPmuIsRtcInitialized_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuIsRtcInitialized_params, out) - OFFSET(NvRmPmuIsRtcInitialized_params, inout));
+
+
+    p_out->ret_ = NvRmPmuIsRtcInitialized( p_in->hRmDevice );
+
+    return err_;
+}
+
+static NvError NvRmPmuWriteRtc_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuWriteRtc_in *p_in;
+    NvRmPmuWriteRtc_out *p_out;
+
+    p_in = (NvRmPmuWriteRtc_in *)InBuffer;
+    p_out = (NvRmPmuWriteRtc_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuWriteRtc_params, out) - OFFSET(NvRmPmuWriteRtc_params, inout));
+
+
+    p_out->ret_ = NvRmPmuWriteRtc( p_in->hRmDevice, p_in->Count );
+
+    return err_;
+}
+
+static NvError NvRmPmuReadRtc_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuReadRtc_in *p_in;
+    NvRmPmuReadRtc_out *p_out;
+
+    p_in = (NvRmPmuReadRtc_in *)InBuffer;
+    p_out = (NvRmPmuReadRtc_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuReadRtc_params, out) - OFFSET(NvRmPmuReadRtc_params, inout));
+
+
+    p_out->ret_ = NvRmPmuReadRtc( p_in->hRmDevice, &p_out->pCount );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetBatteryChemistry_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetBatteryChemistry_in *p_in;
+    NvRmPmuGetBatteryChemistry_out *p_out;
+
+    p_in = (NvRmPmuGetBatteryChemistry_in *)InBuffer;
+    p_out = (NvRmPmuGetBatteryChemistry_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetBatteryChemistry_params, out) - OFFSET(NvRmPmuGetBatteryChemistry_params, inout));
+
+
+    NvRmPmuGetBatteryChemistry( p_in->hRmDevice, p_in->batteryInst, &p_out->pChemistry );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetBatteryFullLifeTime_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetBatteryFullLifeTime_in *p_in;
+    NvRmPmuGetBatteryFullLifeTime_out *p_out;
+
+    p_in = (NvRmPmuGetBatteryFullLifeTime_in *)InBuffer;
+    p_out = (NvRmPmuGetBatteryFullLifeTime_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetBatteryFullLifeTime_params, out) - OFFSET(NvRmPmuGetBatteryFullLifeTime_params, inout));
+
+
+    NvRmPmuGetBatteryFullLifeTime( p_in->hRmDevice, p_in->batteryInst, &p_out->pLifeTime );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetBatteryData_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetBatteryData_in *p_in;
+    NvRmPmuGetBatteryData_out *p_out;
+
+    p_in = (NvRmPmuGetBatteryData_in *)InBuffer;
+    p_out = (NvRmPmuGetBatteryData_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetBatteryData_params, out) - OFFSET(NvRmPmuGetBatteryData_params, inout));
+
+
+    p_out->ret_ = NvRmPmuGetBatteryData( p_in->hRmDevice, p_in->batteryInst, &p_out->pData );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetBatteryStatus_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetBatteryStatus_in *p_in;
+    NvRmPmuGetBatteryStatus_out *p_out;
+
+    p_in = (NvRmPmuGetBatteryStatus_in *)InBuffer;
+    p_out = (NvRmPmuGetBatteryStatus_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetBatteryStatus_params, out) - OFFSET(NvRmPmuGetBatteryStatus_params, inout));
+
+
+    p_out->ret_ = NvRmPmuGetBatteryStatus( p_in->hRmDevice, p_in->batteryInst, &p_out->pStatus );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetAcLineStatus_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetAcLineStatus_in *p_in;
+    NvRmPmuGetAcLineStatus_out *p_out;
+
+    p_in = (NvRmPmuGetAcLineStatus_in *)InBuffer;
+    p_out = (NvRmPmuGetAcLineStatus_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetAcLineStatus_params, out) - OFFSET(NvRmPmuGetAcLineStatus_params, inout));
+
+
+    p_out->ret_ = NvRmPmuGetAcLineStatus( p_in->hRmDevice, &p_out->pStatus );
+
+    return err_;
+}
+
+static NvError NvRmPmuSetChargingCurrentLimit_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuSetChargingCurrentLimit_in *p_in;
+
+    p_in = (NvRmPmuSetChargingCurrentLimit_in *)InBuffer;
+
+
+    NvRmPmuSetChargingCurrentLimit( p_in->hRmDevice, p_in->ChargingPath, p_in->ChargingCurrentLimitMa, p_in->ChargerType );
+
+    return err_;
+}
+
+static NvError NvRmPmuSetSocRailPowerState_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuSetSocRailPowerState_in *p_in;
+
+    p_in = (NvRmPmuSetSocRailPowerState_in *)InBuffer;
+
+
+    NvRmPmuSetSocRailPowerState( p_in->hDevice, p_in->vddId, p_in->Enable );
+
+    return err_;
+}
+
+static NvError NvRmPmuSetVoltage_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuSetVoltage_in *p_in;
+    NvRmPmuSetVoltage_out *p_out;
+
+    p_in = (NvRmPmuSetVoltage_in *)InBuffer;
+    p_out = (NvRmPmuSetVoltage_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuSetVoltage_params, out) - OFFSET(NvRmPmuSetVoltage_params, inout));
+
+
+    NvRmPmuSetVoltage( p_in->hDevice, p_in->vddId, p_in->MilliVolts, &p_out->pSettleMicroSeconds );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetVoltage_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetVoltage_in *p_in;
+    NvRmPmuGetVoltage_out *p_out;
+
+    p_in = (NvRmPmuGetVoltage_in *)InBuffer;
+    p_out = (NvRmPmuGetVoltage_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetVoltage_params, out) - OFFSET(NvRmPmuGetVoltage_params, inout));
+
+
+    NvRmPmuGetVoltage( p_in->hDevice, p_in->vddId, &p_out->pMilliVolts );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetCapabilities_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetCapabilities_in *p_in;
+    NvRmPmuGetCapabilities_out *p_out;
+
+    p_in = (NvRmPmuGetCapabilities_in *)InBuffer;
+    p_out = (NvRmPmuGetCapabilities_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetCapabilities_params, out) - OFFSET(NvRmPmuGetCapabilities_params, inout));
+
+
+    NvRmPmuGetCapabilities( p_in->hDevice, p_in->vddId, &p_out->pCapabilities );
+
+    return err_;
+}
+
+NvError nvrm_pmu_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pmu_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 12:
+        err_ = NvRmPmuIsRtcInitialized_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 11:
+        err_ = NvRmPmuWriteRtc_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 10:
+        err_ = NvRmPmuReadRtc_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 9:
+        err_ = NvRmPmuGetBatteryChemistry_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRmPmuGetBatteryFullLifeTime_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmPmuGetBatteryData_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmPmuGetBatteryStatus_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmPmuGetAcLineStatus_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmPmuSetChargingCurrentLimit_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmPmuSetSocRailPowerState_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmPmuSetVoltage_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmPmuGetVoltage_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmPmuGetCapabilities_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_power_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_power_dispatch.c
new file mode 100644
index 000000000000..cf70ec5a9b45
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_power_dispatch.c
@@ -0,0 +1,1916 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_power.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmKernelPowerResume_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+} NV_ALIGN(4) NvRmKernelPowerResume_in;
+
+typedef struct NvRmKernelPowerResume_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmKernelPowerResume_inout;
+
+typedef struct NvRmKernelPowerResume_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmKernelPowerResume_out;
+
+typedef struct NvRmKernelPowerResume_params_t
+{
+    NvRmKernelPowerResume_in in;
+    NvRmKernelPowerResume_inout inout;
+    NvRmKernelPowerResume_out out;
+} NvRmKernelPowerResume_params;
+
+typedef struct NvRmKernelPowerSuspend_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+} NV_ALIGN(4) NvRmKernelPowerSuspend_in;
+
+typedef struct NvRmKernelPowerSuspend_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmKernelPowerSuspend_inout;
+
+typedef struct NvRmKernelPowerSuspend_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmKernelPowerSuspend_out;
+
+typedef struct NvRmKernelPowerSuspend_params_t
+{
+    NvRmKernelPowerSuspend_in in;
+    NvRmKernelPowerSuspend_inout inout;
+    NvRmKernelPowerSuspend_out out;
+} NvRmKernelPowerSuspend_params;
+
+typedef struct NvRmDfsSetLowVoltageThreshold_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmDfsVoltageRailId RailId;
+    NvRmMilliVolts LowMv;
+} NV_ALIGN(4) NvRmDfsSetLowVoltageThreshold_in;
+
+typedef struct NvRmDfsSetLowVoltageThreshold_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsSetLowVoltageThreshold_inout;
+
+typedef struct NvRmDfsSetLowVoltageThreshold_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsSetLowVoltageThreshold_out;
+
+typedef struct NvRmDfsSetLowVoltageThreshold_params_t
+{
+    NvRmDfsSetLowVoltageThreshold_in in;
+    NvRmDfsSetLowVoltageThreshold_inout inout;
+    NvRmDfsSetLowVoltageThreshold_out out;
+} NvRmDfsSetLowVoltageThreshold_params;
+
+typedef struct NvRmDfsGetLowVoltageThreshold_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmDfsVoltageRailId RailId;
+} NV_ALIGN(4) NvRmDfsGetLowVoltageThreshold_in;
+
+typedef struct NvRmDfsGetLowVoltageThreshold_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsGetLowVoltageThreshold_inout;
+
+typedef struct NvRmDfsGetLowVoltageThreshold_out_t
+{
+    NvRmMilliVolts pLowMv;
+    NvRmMilliVolts pPresentMv;
+} NV_ALIGN(4) NvRmDfsGetLowVoltageThreshold_out;
+
+typedef struct NvRmDfsGetLowVoltageThreshold_params_t
+{
+    NvRmDfsGetLowVoltageThreshold_in in;
+    NvRmDfsGetLowVoltageThreshold_inout inout;
+    NvRmDfsGetLowVoltageThreshold_out out;
+} NvRmDfsGetLowVoltageThreshold_params;
+
+typedef struct NvRmDfsLogBusyGetEntry_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 EntryIndex;
+} NV_ALIGN(4) NvRmDfsLogBusyGetEntry_in;
+
+typedef struct NvRmDfsLogBusyGetEntry_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsLogBusyGetEntry_inout;
+
+typedef struct NvRmDfsLogBusyGetEntry_out_t
+{
+    NvError ret_;
+    NvU32 pSampleIndex;
+    NvU32 pClientId;
+    NvU32 pClientTag;
+    NvRmDfsBusyHint pBusyHint;
+} NV_ALIGN(4) NvRmDfsLogBusyGetEntry_out;
+
+typedef struct NvRmDfsLogBusyGetEntry_params_t
+{
+    NvRmDfsLogBusyGetEntry_in in;
+    NvRmDfsLogBusyGetEntry_inout inout;
+    NvRmDfsLogBusyGetEntry_out out;
+} NvRmDfsLogBusyGetEntry_params;
+
+typedef struct NvRmDfsLogStarvationGetEntry_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 EntryIndex;
+} NV_ALIGN(4) NvRmDfsLogStarvationGetEntry_in;
+
+typedef struct NvRmDfsLogStarvationGetEntry_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsLogStarvationGetEntry_inout;
+
+typedef struct NvRmDfsLogStarvationGetEntry_out_t
+{
+    NvError ret_;
+    NvU32 pSampleIndex;
+    NvU32 pClientId;
+    NvU32 pClientTag;
+    NvRmDfsStarvationHint pStarvationHint;
+} NV_ALIGN(4) NvRmDfsLogStarvationGetEntry_out;
+
+typedef struct NvRmDfsLogStarvationGetEntry_params_t
+{
+    NvRmDfsLogStarvationGetEntry_in in;
+    NvRmDfsLogStarvationGetEntry_inout inout;
+    NvRmDfsLogStarvationGetEntry_out out;
+} NvRmDfsLogStarvationGetEntry_params;
+
+typedef struct NvRmDfsLogActivityGetEntry_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 EntryIndex;
+    NvU32 LogDomainsCount;
+    NvU32  * pActiveCyclesList;
+    NvRmFreqKHz  * pAveragesList;
+    NvRmFreqKHz  * pFrequenciesList;
+} NV_ALIGN(4) NvRmDfsLogActivityGetEntry_in;
+
+typedef struct NvRmDfsLogActivityGetEntry_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsLogActivityGetEntry_inout;
+
+typedef struct NvRmDfsLogActivityGetEntry_out_t
+{
+    NvError ret_;
+    NvU32 pIntervalMs;
+    NvU32 pLp2TimeMs;
+} NV_ALIGN(4) NvRmDfsLogActivityGetEntry_out;
+
+typedef struct NvRmDfsLogActivityGetEntry_params_t
+{
+    NvRmDfsLogActivityGetEntry_in in;
+    NvRmDfsLogActivityGetEntry_inout inout;
+    NvRmDfsLogActivityGetEntry_out out;
+} NvRmDfsLogActivityGetEntry_params;
+
+typedef struct NvRmDfsLogGetMeanFrequencies_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 LogMeanFreqListCount;
+    NvRmFreqKHz  * pLogMeanFreqList;
+} NV_ALIGN(4) NvRmDfsLogGetMeanFrequencies_in;
+
+typedef struct NvRmDfsLogGetMeanFrequencies_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsLogGetMeanFrequencies_inout;
+
+typedef struct NvRmDfsLogGetMeanFrequencies_out_t
+{
+    NvError ret_;
+    NvU32 pLogLp2TimeMs;
+    NvU32 pLogLp2Entries;
+} NV_ALIGN(4) NvRmDfsLogGetMeanFrequencies_out;
+
+typedef struct NvRmDfsLogGetMeanFrequencies_params_t
+{
+    NvRmDfsLogGetMeanFrequencies_in in;
+    NvRmDfsLogGetMeanFrequencies_inout inout;
+    NvRmDfsLogGetMeanFrequencies_out out;
+} NvRmDfsLogGetMeanFrequencies_params;
+
+typedef struct NvRmDfsLogStart_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+} NV_ALIGN(4) NvRmDfsLogStart_in;
+
+typedef struct NvRmDfsLogStart_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsLogStart_inout;
+
+typedef struct NvRmDfsLogStart_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsLogStart_out;
+
+typedef struct NvRmDfsLogStart_params_t
+{
+    NvRmDfsLogStart_in in;
+    NvRmDfsLogStart_inout inout;
+    NvRmDfsLogStart_out out;
+} NvRmDfsLogStart_params;
+
+typedef struct NvRmDfsGetProfileData_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 DfsProfileCount;
+    NvU32  * pSamplesNoList;
+    NvU32  * pProfileTimeUsList;
+} NV_ALIGN(4) NvRmDfsGetProfileData_in;
+
+typedef struct NvRmDfsGetProfileData_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsGetProfileData_inout;
+
+typedef struct NvRmDfsGetProfileData_out_t
+{
+    NvError ret_;
+    NvU32 pDfsPeriodUs;
+} NV_ALIGN(4) NvRmDfsGetProfileData_out;
+
+typedef struct NvRmDfsGetProfileData_params_t
+{
+    NvRmDfsGetProfileData_in in;
+    NvRmDfsGetProfileData_inout inout;
+    NvRmDfsGetProfileData_out out;
+} NvRmDfsGetProfileData_params;
+
+typedef struct NvRmDfsSetAvHighCorner_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmFreqKHz DfsSystemHighKHz;
+    NvRmFreqKHz DfsAvpHighKHz;
+    NvRmFreqKHz DfsVpipeHighKHz;
+} NV_ALIGN(4) NvRmDfsSetAvHighCorner_in;
+
+typedef struct NvRmDfsSetAvHighCorner_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsSetAvHighCorner_inout;
+
+typedef struct NvRmDfsSetAvHighCorner_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDfsSetAvHighCorner_out;
+
+typedef struct NvRmDfsSetAvHighCorner_params_t
+{
+    NvRmDfsSetAvHighCorner_in in;
+    NvRmDfsSetAvHighCorner_inout inout;
+    NvRmDfsSetAvHighCorner_out out;
+} NvRmDfsSetAvHighCorner_params;
+
+typedef struct NvRmDfsSetCpuEmcHighCorner_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmFreqKHz DfsCpuHighKHz;
+    NvRmFreqKHz DfsEmcHighKHz;
+} NV_ALIGN(4) NvRmDfsSetCpuEmcHighCorner_in;
+
+typedef struct NvRmDfsSetCpuEmcHighCorner_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsSetCpuEmcHighCorner_inout;
+
+typedef struct NvRmDfsSetCpuEmcHighCorner_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDfsSetCpuEmcHighCorner_out;
+
+typedef struct NvRmDfsSetCpuEmcHighCorner_params_t
+{
+    NvRmDfsSetCpuEmcHighCorner_in in;
+    NvRmDfsSetCpuEmcHighCorner_inout inout;
+    NvRmDfsSetCpuEmcHighCorner_out out;
+} NvRmDfsSetCpuEmcHighCorner_params;
+
+typedef struct NvRmDfsSetEmcEnvelope_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmFreqKHz DfsEmcLowCornerKHz;
+    NvRmFreqKHz DfsEmcHighCornerKHz;
+} NV_ALIGN(4) NvRmDfsSetEmcEnvelope_in;
+
+typedef struct NvRmDfsSetEmcEnvelope_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsSetEmcEnvelope_inout;
+
+typedef struct NvRmDfsSetEmcEnvelope_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDfsSetEmcEnvelope_out;
+
+typedef struct NvRmDfsSetEmcEnvelope_params_t
+{
+    NvRmDfsSetEmcEnvelope_in in;
+    NvRmDfsSetEmcEnvelope_inout inout;
+    NvRmDfsSetEmcEnvelope_out out;
+} NvRmDfsSetEmcEnvelope_params;
+
+typedef struct NvRmDfsSetCpuEnvelope_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmFreqKHz DfsCpuLowCornerKHz;
+    NvRmFreqKHz DfsCpuHighCornerKHz;
+} NV_ALIGN(4) NvRmDfsSetCpuEnvelope_in;
+
+typedef struct NvRmDfsSetCpuEnvelope_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsSetCpuEnvelope_inout;
+
+typedef struct NvRmDfsSetCpuEnvelope_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDfsSetCpuEnvelope_out;
+
+typedef struct NvRmDfsSetCpuEnvelope_params_t
+{
+    NvRmDfsSetCpuEnvelope_in in;
+    NvRmDfsSetCpuEnvelope_inout inout;
+    NvRmDfsSetCpuEnvelope_out out;
+} NvRmDfsSetCpuEnvelope_params;
+
+typedef struct NvRmDfsSetTarget_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 DfsFreqListCount;
+    NvRmFreqKHz  * pDfsTargetFreqList;
+} NV_ALIGN(4) NvRmDfsSetTarget_in;
+
+typedef struct NvRmDfsSetTarget_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsSetTarget_inout;
+
+typedef struct NvRmDfsSetTarget_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDfsSetTarget_out;
+
+typedef struct NvRmDfsSetTarget_params_t
+{
+    NvRmDfsSetTarget_in in;
+    NvRmDfsSetTarget_inout inout;
+    NvRmDfsSetTarget_out out;
+} NvRmDfsSetTarget_params;
+
+typedef struct NvRmDfsSetLowCorner_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 DfsFreqListCount;
+    NvRmFreqKHz  * pDfsLowFreqList;
+} NV_ALIGN(4) NvRmDfsSetLowCorner_in;
+
+typedef struct NvRmDfsSetLowCorner_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsSetLowCorner_inout;
+
+typedef struct NvRmDfsSetLowCorner_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDfsSetLowCorner_out;
+
+typedef struct NvRmDfsSetLowCorner_params_t
+{
+    NvRmDfsSetLowCorner_in in;
+    NvRmDfsSetLowCorner_inout inout;
+    NvRmDfsSetLowCorner_out out;
+} NvRmDfsSetLowCorner_params;
+
+typedef struct NvRmDfsSetState_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmDfsRunState NewDfsRunState;
+} NV_ALIGN(4) NvRmDfsSetState_in;
+
+typedef struct NvRmDfsSetState_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsSetState_inout;
+
+typedef struct NvRmDfsSetState_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDfsSetState_out;
+
+typedef struct NvRmDfsSetState_params_t
+{
+    NvRmDfsSetState_in in;
+    NvRmDfsSetState_inout inout;
+    NvRmDfsSetState_out out;
+} NvRmDfsSetState_params;
+
+typedef struct NvRmDfsGetClockUtilization_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmDfsClockId ClockId;
+} NV_ALIGN(4) NvRmDfsGetClockUtilization_in;
+
+typedef struct NvRmDfsGetClockUtilization_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsGetClockUtilization_inout;
+
+typedef struct NvRmDfsGetClockUtilization_out_t
+{
+    NvError ret_;
+    NvRmDfsClockUsage pClockUsage;
+} NV_ALIGN(4) NvRmDfsGetClockUtilization_out;
+
+typedef struct NvRmDfsGetClockUtilization_params_t
+{
+    NvRmDfsGetClockUtilization_in in;
+    NvRmDfsGetClockUtilization_inout inout;
+    NvRmDfsGetClockUtilization_out out;
+} NvRmDfsGetClockUtilization_params;
+
+typedef struct NvRmDfsGetState_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+} NV_ALIGN(4) NvRmDfsGetState_in;
+
+typedef struct NvRmDfsGetState_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDfsGetState_inout;
+
+typedef struct NvRmDfsGetState_out_t
+{
+    NvRmDfsRunState ret_;
+} NV_ALIGN(4) NvRmDfsGetState_out;
+
+typedef struct NvRmDfsGetState_params_t
+{
+    NvRmDfsGetState_in in;
+    NvRmDfsGetState_inout inout;
+    NvRmDfsGetState_out out;
+} NvRmDfsGetState_params;
+
+typedef struct NvRmPowerActivityHint_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID ModuleId;
+    NvU32 ClientId;
+    NvU32 ActivityDurationMs;
+} NV_ALIGN(4) NvRmPowerActivityHint_in;
+
+typedef struct NvRmPowerActivityHint_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerActivityHint_inout;
+
+typedef struct NvRmPowerActivityHint_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmPowerActivityHint_out;
+
+typedef struct NvRmPowerActivityHint_params_t
+{
+    NvRmPowerActivityHint_in in;
+    NvRmPowerActivityHint_inout inout;
+    NvRmPowerActivityHint_out out;
+} NvRmPowerActivityHint_params;
+
+typedef struct NvRmPowerStarvationHintMulti_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 ClientId;
+    NvRmDfsStarvationHint  * pMultiHint;
+    NvU32 NumHints;
+} NV_ALIGN(4) NvRmPowerStarvationHintMulti_in;
+
+typedef struct NvRmPowerStarvationHintMulti_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerStarvationHintMulti_inout;
+
+typedef struct NvRmPowerStarvationHintMulti_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmPowerStarvationHintMulti_out;
+
+typedef struct NvRmPowerStarvationHintMulti_params_t
+{
+    NvRmPowerStarvationHintMulti_in in;
+    NvRmPowerStarvationHintMulti_inout inout;
+    NvRmPowerStarvationHintMulti_out out;
+} NvRmPowerStarvationHintMulti_params;
+
+typedef struct NvRmPowerStarvationHint_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmDfsClockId ClockId;
+    NvU32 ClientId;
+    NvBool Starving;
+} NV_ALIGN(4) NvRmPowerStarvationHint_in;
+
+typedef struct NvRmPowerStarvationHint_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerStarvationHint_inout;
+
+typedef struct NvRmPowerStarvationHint_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmPowerStarvationHint_out;
+
+typedef struct NvRmPowerStarvationHint_params_t
+{
+    NvRmPowerStarvationHint_in in;
+    NvRmPowerStarvationHint_inout inout;
+    NvRmPowerStarvationHint_out out;
+} NvRmPowerStarvationHint_params;
+
+typedef struct NvRmPowerBusyHintMulti_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 ClientId;
+    NvRmDfsBusyHint  * pMultiHint;
+    NvU32 NumHints;
+    NvRmDfsBusyHintSyncMode Mode;
+} NV_ALIGN(4) NvRmPowerBusyHintMulti_in;
+
+typedef struct NvRmPowerBusyHintMulti_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerBusyHintMulti_inout;
+
+typedef struct NvRmPowerBusyHintMulti_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmPowerBusyHintMulti_out;
+
+typedef struct NvRmPowerBusyHintMulti_params_t
+{
+    NvRmPowerBusyHintMulti_in in;
+    NvRmPowerBusyHintMulti_inout inout;
+    NvRmPowerBusyHintMulti_out out;
+} NvRmPowerBusyHintMulti_params;
+
+typedef struct NvRmPowerBusyHint_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmDfsClockId ClockId;
+    NvU32 ClientId;
+    NvU32 BoostDurationMs;
+    NvRmFreqKHz BoostKHz;
+} NV_ALIGN(4) NvRmPowerBusyHint_in;
+
+typedef struct NvRmPowerBusyHint_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerBusyHint_inout;
+
+typedef struct NvRmPowerBusyHint_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmPowerBusyHint_out;
+
+typedef struct NvRmPowerBusyHint_params_t
+{
+    NvRmPowerBusyHint_in in;
+    NvRmPowerBusyHint_inout inout;
+    NvRmPowerBusyHint_out out;
+} NvRmPowerBusyHint_params;
+
+typedef struct NvRmListPowerAwareModules_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID  * pIdList;
+    NvBool  * pActiveList;
+} NV_ALIGN(4) NvRmListPowerAwareModules_in;
+
+typedef struct NvRmListPowerAwareModules_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmListPowerAwareModules_inout;
+
+typedef struct NvRmListPowerAwareModules_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmListPowerAwareModules_out;
+
+typedef struct NvRmListPowerAwareModules_params_t
+{
+    NvRmListPowerAwareModules_in in;
+    NvRmListPowerAwareModules_inout inout;
+    NvRmListPowerAwareModules_out out;
+} NvRmListPowerAwareModules_params;
+
+typedef struct NvRmPowerVoltageControl_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID ModuleId;
+    NvU32 ClientId;
+    NvRmMilliVolts MinVolts;
+    NvRmMilliVolts MaxVolts;
+    NvRmMilliVolts  * PrefVoltageList;
+    NvU32 PrefVoltageListCount;
+} NV_ALIGN(4) NvRmPowerVoltageControl_in;
+
+typedef struct NvRmPowerVoltageControl_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerVoltageControl_inout;
+
+typedef struct NvRmPowerVoltageControl_out_t
+{
+    NvError ret_;
+    NvRmMilliVolts CurrentVolts;
+} NV_ALIGN(4) NvRmPowerVoltageControl_out;
+
+typedef struct NvRmPowerVoltageControl_params_t
+{
+    NvRmPowerVoltageControl_in in;
+    NvRmPowerVoltageControl_inout inout;
+    NvRmPowerVoltageControl_out out;
+} NvRmPowerVoltageControl_params;
+
+typedef struct NvRmPowerModuleClockControl_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID ModuleId;
+    NvU32 ClientId;
+    NvBool Enable;
+} NV_ALIGN(4) NvRmPowerModuleClockControl_in;
+
+typedef struct NvRmPowerModuleClockControl_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerModuleClockControl_inout;
+
+typedef struct NvRmPowerModuleClockControl_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmPowerModuleClockControl_out;
+
+typedef struct NvRmPowerModuleClockControl_params_t
+{
+    NvRmPowerModuleClockControl_in in;
+    NvRmPowerModuleClockControl_inout inout;
+    NvRmPowerModuleClockControl_out out;
+} NvRmPowerModuleClockControl_params;
+
+typedef struct NvRmPowerModuleClockConfig_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID ModuleId;
+    NvU32 ClientId;
+    NvRmFreqKHz MinFreq;
+    NvRmFreqKHz MaxFreq;
+    NvRmFreqKHz  * PrefFreqList;
+    NvU32 PrefFreqListCount;
+    NvU32 flags;
+} NV_ALIGN(4) NvRmPowerModuleClockConfig_in;
+
+typedef struct NvRmPowerModuleClockConfig_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerModuleClockConfig_inout;
+
+typedef struct NvRmPowerModuleClockConfig_out_t
+{
+    NvError ret_;
+    NvRmFreqKHz CurrentFreq;
+} NV_ALIGN(4) NvRmPowerModuleClockConfig_out;
+
+typedef struct NvRmPowerModuleClockConfig_params_t
+{
+    NvRmPowerModuleClockConfig_in in;
+    NvRmPowerModuleClockConfig_inout inout;
+    NvRmPowerModuleClockConfig_out out;
+} NvRmPowerModuleClockConfig_params;
+
+typedef struct NvRmPowerModuleGetMaxFrequency_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID ModuleId;
+} NV_ALIGN(4) NvRmPowerModuleGetMaxFrequency_in;
+
+typedef struct NvRmPowerModuleGetMaxFrequency_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerModuleGetMaxFrequency_inout;
+
+typedef struct NvRmPowerModuleGetMaxFrequency_out_t
+{
+    NvRmFreqKHz ret_;
+} NV_ALIGN(4) NvRmPowerModuleGetMaxFrequency_out;
+
+typedef struct NvRmPowerModuleGetMaxFrequency_params_t
+{
+    NvRmPowerModuleGetMaxFrequency_in in;
+    NvRmPowerModuleGetMaxFrequency_inout inout;
+    NvRmPowerModuleGetMaxFrequency_out out;
+} NvRmPowerModuleGetMaxFrequency_params;
+
+typedef struct NvRmPowerGetPrimaryFrequency_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+} NV_ALIGN(4) NvRmPowerGetPrimaryFrequency_in;
+
+typedef struct NvRmPowerGetPrimaryFrequency_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerGetPrimaryFrequency_inout;
+
+typedef struct NvRmPowerGetPrimaryFrequency_out_t
+{
+    NvRmFreqKHz ret_;
+} NV_ALIGN(4) NvRmPowerGetPrimaryFrequency_out;
+
+typedef struct NvRmPowerGetPrimaryFrequency_params_t
+{
+    NvRmPowerGetPrimaryFrequency_in in;
+    NvRmPowerGetPrimaryFrequency_inout inout;
+    NvRmPowerGetPrimaryFrequency_out out;
+} NvRmPowerGetPrimaryFrequency_params;
+
+typedef struct NvRmPowerGetState_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+} NV_ALIGN(4) NvRmPowerGetState_in;
+
+typedef struct NvRmPowerGetState_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerGetState_inout;
+
+typedef struct NvRmPowerGetState_out_t
+{
+    NvError ret_;
+    NvRmPowerState pState;
+} NV_ALIGN(4) NvRmPowerGetState_out;
+
+typedef struct NvRmPowerGetState_params_t
+{
+    NvRmPowerGetState_in in;
+    NvRmPowerGetState_inout inout;
+    NvRmPowerGetState_out out;
+} NvRmPowerGetState_params;
+
+typedef struct NvRmPowerEventNotify_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmPowerEvent Event;
+} NV_ALIGN(4) NvRmPowerEventNotify_in;
+
+typedef struct NvRmPowerEventNotify_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerEventNotify_inout;
+
+typedef struct NvRmPowerEventNotify_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerEventNotify_out;
+
+typedef struct NvRmPowerEventNotify_params_t
+{
+    NvRmPowerEventNotify_in in;
+    NvRmPowerEventNotify_inout inout;
+    NvRmPowerEventNotify_out out;
+} NvRmPowerEventNotify_params;
+
+typedef struct NvRmPowerGetEvent_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 ClientId;
+} NV_ALIGN(4) NvRmPowerGetEvent_in;
+
+typedef struct NvRmPowerGetEvent_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerGetEvent_inout;
+
+typedef struct NvRmPowerGetEvent_out_t
+{
+    NvError ret_;
+    NvRmPowerEvent pEvent;
+} NV_ALIGN(4) NvRmPowerGetEvent_out;
+
+typedef struct NvRmPowerGetEvent_params_t
+{
+    NvRmPowerGetEvent_in in;
+    NvRmPowerGetEvent_inout inout;
+    NvRmPowerGetEvent_out out;
+} NvRmPowerGetEvent_params;
+
+typedef struct NvRmPowerUnRegister_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 ClientId;
+} NV_ALIGN(4) NvRmPowerUnRegister_in;
+
+typedef struct NvRmPowerUnRegister_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerUnRegister_inout;
+
+typedef struct NvRmPowerUnRegister_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerUnRegister_out;
+
+typedef struct NvRmPowerUnRegister_params_t
+{
+    NvRmPowerUnRegister_in in;
+    NvRmPowerUnRegister_inout inout;
+    NvRmPowerUnRegister_out out;
+} NvRmPowerUnRegister_params;
+
+typedef struct NvRmPowerRegister_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvOsSemaphoreHandle hEventSemaphore;
+} NV_ALIGN(4) NvRmPowerRegister_in;
+
+typedef struct NvRmPowerRegister_inout_t
+{
+    NvU32 pClientId;
+} NV_ALIGN(4) NvRmPowerRegister_inout;
+
+typedef struct NvRmPowerRegister_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmPowerRegister_out;
+
+typedef struct NvRmPowerRegister_params_t
+{
+    NvRmPowerRegister_in in;
+    NvRmPowerRegister_inout inout;
+    NvRmPowerRegister_out out;
+} NvRmPowerRegister_params;
+
+static NvError NvRmKernelPowerResume_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmKernelPowerResume_in *p_in;
+    NvRmKernelPowerResume_out *p_out;
+
+    p_in = (NvRmKernelPowerResume_in *)InBuffer;
+    p_out = (NvRmKernelPowerResume_out *)((NvU8 *)OutBuffer + OFFSET(NvRmKernelPowerResume_params, out) - OFFSET(NvRmKernelPowerResume_params, inout));
+
+
+    p_out->ret_ = NvRmKernelPowerResume( p_in->hRmDeviceHandle );
+
+    return err_;
+}
+
+static NvError NvRmKernelPowerSuspend_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmKernelPowerSuspend_in *p_in;
+    NvRmKernelPowerSuspend_out *p_out;
+
+    p_in = (NvRmKernelPowerSuspend_in *)InBuffer;
+    p_out = (NvRmKernelPowerSuspend_out *)((NvU8 *)OutBuffer + OFFSET(NvRmKernelPowerSuspend_params, out) - OFFSET(NvRmKernelPowerSuspend_params, inout));
+
+
+    p_out->ret_ = NvRmKernelPowerSuspend( p_in->hRmDeviceHandle );
+
+    return err_;
+}
+
+static NvError NvRmDfsSetLowVoltageThreshold_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsSetLowVoltageThreshold_in *p_in;
+
+    p_in = (NvRmDfsSetLowVoltageThreshold_in *)InBuffer;
+
+
+    NvRmDfsSetLowVoltageThreshold( p_in->hRmDeviceHandle, p_in->RailId, p_in->LowMv );
+
+    return err_;
+}
+
+static NvError NvRmDfsGetLowVoltageThreshold_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsGetLowVoltageThreshold_in *p_in;
+    NvRmDfsGetLowVoltageThreshold_out *p_out;
+
+    p_in = (NvRmDfsGetLowVoltageThreshold_in *)InBuffer;
+    p_out = (NvRmDfsGetLowVoltageThreshold_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsGetLowVoltageThreshold_params, out) - OFFSET(NvRmDfsGetLowVoltageThreshold_params, inout));
+
+
+    NvRmDfsGetLowVoltageThreshold( p_in->hRmDeviceHandle, p_in->RailId, &p_out->pLowMv, &p_out->pPresentMv );
+
+    return err_;
+}
+
+static NvError NvRmDfsLogBusyGetEntry_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsLogBusyGetEntry_in *p_in;
+    NvRmDfsLogBusyGetEntry_out *p_out;
+
+    p_in = (NvRmDfsLogBusyGetEntry_in *)InBuffer;
+    p_out = (NvRmDfsLogBusyGetEntry_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsLogBusyGetEntry_params, out) - OFFSET(NvRmDfsLogBusyGetEntry_params, inout));
+
+
+    p_out->ret_ = NvRmDfsLogBusyGetEntry( p_in->hRmDeviceHandle, p_in->EntryIndex, &p_out->pSampleIndex, &p_out->pClientId, &p_out->pClientTag, &p_out->pBusyHint );
+
+    return err_;
+}
+
+static NvError NvRmDfsLogStarvationGetEntry_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsLogStarvationGetEntry_in *p_in;
+    NvRmDfsLogStarvationGetEntry_out *p_out;
+
+    p_in = (NvRmDfsLogStarvationGetEntry_in *)InBuffer;
+    p_out = (NvRmDfsLogStarvationGetEntry_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsLogStarvationGetEntry_params, out) - OFFSET(NvRmDfsLogStarvationGetEntry_params, inout));
+
+
+    p_out->ret_ = NvRmDfsLogStarvationGetEntry( p_in->hRmDeviceHandle, p_in->EntryIndex, &p_out->pSampleIndex, &p_out->pClientId, &p_out->pClientTag, &p_out->pStarvationHint );
+
+    return err_;
+}
+
+static NvError NvRmDfsLogActivityGetEntry_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsLogActivityGetEntry_in *p_in;
+    NvRmDfsLogActivityGetEntry_out *p_out;
+    NvU32  *pActiveCyclesList = NULL;
+    NvRmFreqKHz *pAveragesList = NULL;
+    NvRmFreqKHz *pFrequenciesList = NULL;
+
+    p_in = (NvRmDfsLogActivityGetEntry_in *)InBuffer;
+    p_out = (NvRmDfsLogActivityGetEntry_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsLogActivityGetEntry_params, out) - OFFSET(NvRmDfsLogActivityGetEntry_params, inout));
+
+    if( p_in->LogDomainsCount && p_in->pActiveCyclesList )
+    {
+        pActiveCyclesList = (NvU32  *)NvOsAlloc( p_in->LogDomainsCount * sizeof( NvU32  ) );
+        if( !pActiveCyclesList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+    if( p_in->LogDomainsCount && p_in->pAveragesList )
+    {
+        pAveragesList = (NvRmFreqKHz  *)NvOsAlloc( p_in->LogDomainsCount * sizeof( NvRmFreqKHz  ) );
+        if( !pAveragesList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+    if( p_in->LogDomainsCount && p_in->pFrequenciesList )
+    {
+        pFrequenciesList = (NvRmFreqKHz  *)NvOsAlloc( p_in->LogDomainsCount * sizeof( NvRmFreqKHz  ) );
+        if( !pFrequenciesList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDfsLogActivityGetEntry( p_in->hRmDeviceHandle, p_in->EntryIndex, p_in->LogDomainsCount, &p_out->pIntervalMs, &p_out->pLp2TimeMs, pActiveCyclesList, pAveragesList, pFrequenciesList );
+
+    if(p_in->pActiveCyclesList && pActiveCyclesList)
+    {
+        err_ = NvOsCopyOut( p_in->pActiveCyclesList, pActiveCyclesList, p_in->LogDomainsCount * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+    if(p_in->pAveragesList && pAveragesList)
+    {
+        err_ = NvOsCopyOut( p_in->pAveragesList, pAveragesList, p_in->LogDomainsCount * sizeof( NvRmFreqKHz  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+    if(p_in->pFrequenciesList && pFrequenciesList)
+    {
+        err_ = NvOsCopyOut( p_in->pFrequenciesList, pFrequenciesList, p_in->LogDomainsCount * sizeof( NvRmFreqKHz  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pActiveCyclesList );
+    NvOsFree( pAveragesList );
+    NvOsFree( pFrequenciesList );
+    return err_;
+}
+
+static NvError NvRmDfsLogGetMeanFrequencies_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsLogGetMeanFrequencies_in *p_in;
+    NvRmDfsLogGetMeanFrequencies_out *p_out;
+    NvRmFreqKHz *pLogMeanFreqList = NULL;
+
+    p_in = (NvRmDfsLogGetMeanFrequencies_in *)InBuffer;
+    p_out = (NvRmDfsLogGetMeanFrequencies_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsLogGetMeanFrequencies_params, out) - OFFSET(NvRmDfsLogGetMeanFrequencies_params, inout));
+
+    if( p_in->LogMeanFreqListCount && p_in->pLogMeanFreqList )
+    {
+        pLogMeanFreqList = (NvRmFreqKHz  *)NvOsAlloc( p_in->LogMeanFreqListCount * sizeof( NvRmFreqKHz  ) );
+        if( !pLogMeanFreqList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDfsLogGetMeanFrequencies( p_in->hRmDeviceHandle, p_in->LogMeanFreqListCount, pLogMeanFreqList, &p_out->pLogLp2TimeMs, &p_out->pLogLp2Entries );
+
+    if(p_in->pLogMeanFreqList && pLogMeanFreqList)
+    {
+        err_ = NvOsCopyOut( p_in->pLogMeanFreqList, pLogMeanFreqList, p_in->LogMeanFreqListCount * sizeof( NvRmFreqKHz  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pLogMeanFreqList );
+    return err_;
+}
+
+static NvError NvRmDfsLogStart_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsLogStart_in *p_in;
+
+    p_in = (NvRmDfsLogStart_in *)InBuffer;
+
+
+    NvRmDfsLogStart( p_in->hRmDeviceHandle );
+
+    return err_;
+}
+
+static NvError NvRmDfsGetProfileData_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsGetProfileData_in *p_in;
+    NvRmDfsGetProfileData_out *p_out;
+    NvU32  *pSamplesNoList = NULL;
+    NvU32  *pProfileTimeUsList = NULL;
+
+    p_in = (NvRmDfsGetProfileData_in *)InBuffer;
+    p_out = (NvRmDfsGetProfileData_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsGetProfileData_params, out) - OFFSET(NvRmDfsGetProfileData_params, inout));
+
+    if( p_in->DfsProfileCount && p_in->pSamplesNoList )
+    {
+        pSamplesNoList = (NvU32  *)NvOsAlloc( p_in->DfsProfileCount * sizeof( NvU32  ) );
+        if( !pSamplesNoList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+    if( p_in->DfsProfileCount && p_in->pProfileTimeUsList )
+    {
+        pProfileTimeUsList = (NvU32  *)NvOsAlloc( p_in->DfsProfileCount * sizeof( NvU32  ) );
+        if( !pProfileTimeUsList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDfsGetProfileData( p_in->hRmDeviceHandle, p_in->DfsProfileCount, pSamplesNoList, pProfileTimeUsList, &p_out->pDfsPeriodUs );
+
+    if(p_in->pSamplesNoList && pSamplesNoList)
+    {
+        err_ = NvOsCopyOut( p_in->pSamplesNoList, pSamplesNoList, p_in->DfsProfileCount * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+    if(p_in->pProfileTimeUsList && pProfileTimeUsList)
+    {
+        err_ = NvOsCopyOut( p_in->pProfileTimeUsList, pProfileTimeUsList, p_in->DfsProfileCount * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pSamplesNoList );
+    NvOsFree( pProfileTimeUsList );
+    return err_;
+}
+
+static NvError NvRmDfsSetAvHighCorner_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsSetAvHighCorner_in *p_in;
+    NvRmDfsSetAvHighCorner_out *p_out;
+
+    p_in = (NvRmDfsSetAvHighCorner_in *)InBuffer;
+    p_out = (NvRmDfsSetAvHighCorner_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsSetAvHighCorner_params, out) - OFFSET(NvRmDfsSetAvHighCorner_params, inout));
+
+
+    p_out->ret_ = NvRmDfsSetAvHighCorner( p_in->hRmDeviceHandle, p_in->DfsSystemHighKHz, p_in->DfsAvpHighKHz, p_in->DfsVpipeHighKHz );
+
+    return err_;
+}
+
+static NvError NvRmDfsSetCpuEmcHighCorner_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsSetCpuEmcHighCorner_in *p_in;
+    NvRmDfsSetCpuEmcHighCorner_out *p_out;
+
+    p_in = (NvRmDfsSetCpuEmcHighCorner_in *)InBuffer;
+    p_out = (NvRmDfsSetCpuEmcHighCorner_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsSetCpuEmcHighCorner_params, out) - OFFSET(NvRmDfsSetCpuEmcHighCorner_params, inout));
+
+
+    p_out->ret_ = NvRmDfsSetCpuEmcHighCorner( p_in->hRmDeviceHandle, p_in->DfsCpuHighKHz, p_in->DfsEmcHighKHz );
+
+    return err_;
+}
+
+static NvError NvRmDfsSetEmcEnvelope_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsSetEmcEnvelope_in *p_in;
+    NvRmDfsSetEmcEnvelope_out *p_out;
+
+    p_in = (NvRmDfsSetEmcEnvelope_in *)InBuffer;
+    p_out = (NvRmDfsSetEmcEnvelope_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsSetEmcEnvelope_params, out) - OFFSET(NvRmDfsSetEmcEnvelope_params, inout));
+
+
+    p_out->ret_ = NvRmDfsSetEmcEnvelope( p_in->hRmDeviceHandle, p_in->DfsEmcLowCornerKHz, p_in->DfsEmcHighCornerKHz );
+
+    return err_;
+}
+
+static NvError NvRmDfsSetCpuEnvelope_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsSetCpuEnvelope_in *p_in;
+    NvRmDfsSetCpuEnvelope_out *p_out;
+
+    p_in = (NvRmDfsSetCpuEnvelope_in *)InBuffer;
+    p_out = (NvRmDfsSetCpuEnvelope_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsSetCpuEnvelope_params, out) - OFFSET(NvRmDfsSetCpuEnvelope_params, inout));
+
+
+    p_out->ret_ = NvRmDfsSetCpuEnvelope( p_in->hRmDeviceHandle, p_in->DfsCpuLowCornerKHz, p_in->DfsCpuHighCornerKHz );
+
+    return err_;
+}
+
+static NvError NvRmDfsSetTarget_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsSetTarget_in *p_in;
+    NvRmDfsSetTarget_out *p_out;
+    NvRmFreqKHz *pDfsTargetFreqList = NULL;
+
+    p_in = (NvRmDfsSetTarget_in *)InBuffer;
+    p_out = (NvRmDfsSetTarget_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsSetTarget_params, out) - OFFSET(NvRmDfsSetTarget_params, inout));
+
+    if( p_in->DfsFreqListCount && p_in->pDfsTargetFreqList )
+    {
+        pDfsTargetFreqList = (NvRmFreqKHz  *)NvOsAlloc( p_in->DfsFreqListCount * sizeof( NvRmFreqKHz  ) );
+        if( !pDfsTargetFreqList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pDfsTargetFreqList )
+        {
+            err_ = NvOsCopyIn( pDfsTargetFreqList, p_in->pDfsTargetFreqList, p_in->DfsFreqListCount * sizeof( NvRmFreqKHz  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmDfsSetTarget( p_in->hRmDeviceHandle, p_in->DfsFreqListCount, pDfsTargetFreqList );
+
+clean:
+    NvOsFree( pDfsTargetFreqList );
+    return err_;
+}
+
+static NvError NvRmDfsSetLowCorner_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsSetLowCorner_in *p_in;
+    NvRmDfsSetLowCorner_out *p_out;
+    NvRmFreqKHz *pDfsLowFreqList = NULL;
+
+    p_in = (NvRmDfsSetLowCorner_in *)InBuffer;
+    p_out = (NvRmDfsSetLowCorner_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsSetLowCorner_params, out) - OFFSET(NvRmDfsSetLowCorner_params, inout));
+
+    if( p_in->DfsFreqListCount && p_in->pDfsLowFreqList )
+    {
+        pDfsLowFreqList = (NvRmFreqKHz  *)NvOsAlloc( p_in->DfsFreqListCount * sizeof( NvRmFreqKHz  ) );
+        if( !pDfsLowFreqList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pDfsLowFreqList )
+        {
+            err_ = NvOsCopyIn( pDfsLowFreqList, p_in->pDfsLowFreqList, p_in->DfsFreqListCount * sizeof( NvRmFreqKHz  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmDfsSetLowCorner( p_in->hRmDeviceHandle, p_in->DfsFreqListCount, pDfsLowFreqList );
+
+clean:
+    NvOsFree( pDfsLowFreqList );
+    return err_;
+}
+
+static NvError NvRmDfsSetState_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsSetState_in *p_in;
+    NvRmDfsSetState_out *p_out;
+
+    p_in = (NvRmDfsSetState_in *)InBuffer;
+    p_out = (NvRmDfsSetState_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsSetState_params, out) - OFFSET(NvRmDfsSetState_params, inout));
+
+
+    p_out->ret_ = NvRmDfsSetState( p_in->hRmDeviceHandle, p_in->NewDfsRunState );
+
+    return err_;
+}
+
+static NvError NvRmDfsGetClockUtilization_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsGetClockUtilization_in *p_in;
+    NvRmDfsGetClockUtilization_out *p_out;
+
+    p_in = (NvRmDfsGetClockUtilization_in *)InBuffer;
+    p_out = (NvRmDfsGetClockUtilization_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsGetClockUtilization_params, out) - OFFSET(NvRmDfsGetClockUtilization_params, inout));
+
+
+    p_out->ret_ = NvRmDfsGetClockUtilization( p_in->hRmDeviceHandle, p_in->ClockId, &p_out->pClockUsage );
+
+    return err_;
+}
+
+static NvError NvRmDfsGetState_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDfsGetState_in *p_in;
+    NvRmDfsGetState_out *p_out;
+
+    p_in = (NvRmDfsGetState_in *)InBuffer;
+    p_out = (NvRmDfsGetState_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDfsGetState_params, out) - OFFSET(NvRmDfsGetState_params, inout));
+
+
+    p_out->ret_ = NvRmDfsGetState( p_in->hRmDeviceHandle );
+
+    return err_;
+}
+
+static NvError NvRmPowerActivityHint_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerActivityHint_in *p_in;
+    NvRmPowerActivityHint_out *p_out;
+
+    p_in = (NvRmPowerActivityHint_in *)InBuffer;
+    p_out = (NvRmPowerActivityHint_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerActivityHint_params, out) - OFFSET(NvRmPowerActivityHint_params, inout));
+
+
+    p_out->ret_ = NvRmPowerActivityHint( p_in->hRmDeviceHandle, p_in->ModuleId, p_in->ClientId, p_in->ActivityDurationMs );
+
+    return err_;
+}
+
+static NvError NvRmPowerStarvationHintMulti_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerStarvationHintMulti_in *p_in;
+    NvRmPowerStarvationHintMulti_out *p_out;
+    NvRmDfsStarvationHint *pMultiHint = NULL;
+
+    p_in = (NvRmPowerStarvationHintMulti_in *)InBuffer;
+    p_out = (NvRmPowerStarvationHintMulti_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerStarvationHintMulti_params, out) - OFFSET(NvRmPowerStarvationHintMulti_params, inout));
+
+    if( p_in->NumHints && p_in->pMultiHint )
+    {
+        pMultiHint = (NvRmDfsStarvationHint  *)NvOsAlloc( p_in->NumHints * sizeof( NvRmDfsStarvationHint  ) );
+        if( !pMultiHint )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pMultiHint )
+        {
+            err_ = NvOsCopyIn( pMultiHint, p_in->pMultiHint, p_in->NumHints * sizeof( NvRmDfsStarvationHint  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmPowerStarvationHintMulti( p_in->hRmDeviceHandle, p_in->ClientId, pMultiHint, p_in->NumHints );
+
+clean:
+    NvOsFree( pMultiHint );
+    return err_;
+}
+
+static NvError NvRmPowerStarvationHint_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerStarvationHint_in *p_in;
+    NvRmPowerStarvationHint_out *p_out;
+
+    p_in = (NvRmPowerStarvationHint_in *)InBuffer;
+    p_out = (NvRmPowerStarvationHint_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerStarvationHint_params, out) - OFFSET(NvRmPowerStarvationHint_params, inout));
+
+
+    p_out->ret_ = NvRmPowerStarvationHint( p_in->hRmDeviceHandle, p_in->ClockId, p_in->ClientId, p_in->Starving );
+
+    return err_;
+}
+
+static NvError NvRmPowerBusyHintMulti_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerBusyHintMulti_in *p_in;
+    NvRmPowerBusyHintMulti_out *p_out;
+    NvRmDfsBusyHint *pMultiHint = NULL;
+
+    p_in = (NvRmPowerBusyHintMulti_in *)InBuffer;
+    p_out = (NvRmPowerBusyHintMulti_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerBusyHintMulti_params, out) - OFFSET(NvRmPowerBusyHintMulti_params, inout));
+
+    if( p_in->NumHints && p_in->pMultiHint )
+    {
+        pMultiHint = (NvRmDfsBusyHint  *)NvOsAlloc( p_in->NumHints * sizeof( NvRmDfsBusyHint  ) );
+        if( !pMultiHint )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pMultiHint )
+        {
+            err_ = NvOsCopyIn( pMultiHint, p_in->pMultiHint, p_in->NumHints * sizeof( NvRmDfsBusyHint  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmPowerBusyHintMulti( p_in->hRmDeviceHandle, p_in->ClientId, pMultiHint, p_in->NumHints, p_in->Mode );
+
+clean:
+    NvOsFree( pMultiHint );
+    return err_;
+}
+
+static NvError NvRmPowerBusyHint_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerBusyHint_in *p_in;
+    NvRmPowerBusyHint_out *p_out;
+
+    p_in = (NvRmPowerBusyHint_in *)InBuffer;
+    p_out = (NvRmPowerBusyHint_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerBusyHint_params, out) - OFFSET(NvRmPowerBusyHint_params, inout));
+
+
+    p_out->ret_ = NvRmPowerBusyHint( p_in->hRmDeviceHandle, p_in->ClockId, p_in->ClientId, p_in->BoostDurationMs, p_in->BoostKHz );
+
+    return err_;
+}
+
+static NvError NvRmListPowerAwareModules_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmListPowerAwareModules_in *p_in;
+    NvRmListPowerAwareModules_inout *p_inout;
+    NvRmListPowerAwareModules_inout inout;
+    NvRmModuleID *pIdList = NULL;
+    NvBool  *pActiveList = NULL;
+
+    p_in = (NvRmListPowerAwareModules_in *)InBuffer;
+    p_inout = (NvRmListPowerAwareModules_inout *)((NvU8 *)InBuffer + OFFSET(NvRmListPowerAwareModules_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->pIdList )
+    {
+        pIdList = (NvRmModuleID  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmModuleID  ) );
+        if( !pIdList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+    if( p_inout->pListSize && p_in->pActiveList )
+    {
+        pActiveList = (NvBool  *)NvOsAlloc( p_inout->pListSize * sizeof( NvBool  ) );
+        if( !pActiveList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    NvRmListPowerAwareModules( p_in->hRmDeviceHandle, &inout.pListSize, pIdList, pActiveList );
+
+
+    p_inout = (NvRmListPowerAwareModules_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->pIdList && pIdList)
+    {
+        err_ = NvOsCopyOut( p_in->pIdList, pIdList, p_inout->pListSize * sizeof( NvRmModuleID  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+    if(p_in->pActiveList && pActiveList)
+    {
+        err_ = NvOsCopyOut( p_in->pActiveList, pActiveList, p_inout->pListSize * sizeof( NvBool  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pIdList );
+    NvOsFree( pActiveList );
+    return err_;
+}
+
+static NvError NvRmPowerVoltageControl_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerVoltageControl_in *p_in;
+    NvRmPowerVoltageControl_out *p_out;
+    NvRmMilliVolts *PrefVoltageList = NULL;
+
+    p_in = (NvRmPowerVoltageControl_in *)InBuffer;
+    p_out = (NvRmPowerVoltageControl_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerVoltageControl_params, out) - OFFSET(NvRmPowerVoltageControl_params, inout));
+
+    if( p_in->PrefVoltageListCount && p_in->PrefVoltageList )
+    {
+        PrefVoltageList = (NvRmMilliVolts  *)NvOsAlloc( p_in->PrefVoltageListCount * sizeof( NvRmMilliVolts  ) );
+        if( !PrefVoltageList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->PrefVoltageList )
+        {
+            err_ = NvOsCopyIn( PrefVoltageList, p_in->PrefVoltageList, p_in->PrefVoltageListCount * sizeof( NvRmMilliVolts  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmPowerVoltageControl( p_in->hRmDeviceHandle, p_in->ModuleId, p_in->ClientId, p_in->MinVolts, p_in->MaxVolts, PrefVoltageList, p_in->PrefVoltageListCount, &p_out->CurrentVolts );
+
+clean:
+    NvOsFree( PrefVoltageList );
+    return err_;
+}
+
+static NvError NvRmPowerModuleClockControl_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerModuleClockControl_in *p_in;
+    NvRmPowerModuleClockControl_out *p_out;
+
+    p_in = (NvRmPowerModuleClockControl_in *)InBuffer;
+    p_out = (NvRmPowerModuleClockControl_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerModuleClockControl_params, out) - OFFSET(NvRmPowerModuleClockControl_params, inout));
+
+
+    p_out->ret_ = NvRmPowerModuleClockControl( p_in->hRmDeviceHandle, p_in->ModuleId, p_in->ClientId, p_in->Enable );
+
+    return err_;
+}
+
+static NvError NvRmPowerModuleClockConfig_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerModuleClockConfig_in *p_in;
+    NvRmPowerModuleClockConfig_out *p_out;
+    NvRmFreqKHz *PrefFreqList = NULL;
+
+    p_in = (NvRmPowerModuleClockConfig_in *)InBuffer;
+    p_out = (NvRmPowerModuleClockConfig_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerModuleClockConfig_params, out) - OFFSET(NvRmPowerModuleClockConfig_params, inout));
+
+    if( p_in->PrefFreqListCount && p_in->PrefFreqList )
+    {
+        PrefFreqList = (NvRmFreqKHz  *)NvOsAlloc( p_in->PrefFreqListCount * sizeof( NvRmFreqKHz  ) );
+        if( !PrefFreqList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->PrefFreqList )
+        {
+            err_ = NvOsCopyIn( PrefFreqList, p_in->PrefFreqList, p_in->PrefFreqListCount * sizeof( NvRmFreqKHz  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmPowerModuleClockConfig( p_in->hRmDeviceHandle, p_in->ModuleId, p_in->ClientId, p_in->MinFreq, p_in->MaxFreq, PrefFreqList, p_in->PrefFreqListCount, &p_out->CurrentFreq, p_in->flags );
+
+clean:
+    NvOsFree( PrefFreqList );
+    return err_;
+}
+
+static NvError NvRmPowerModuleGetMaxFrequency_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerModuleGetMaxFrequency_in *p_in;
+    NvRmPowerModuleGetMaxFrequency_out *p_out;
+
+    p_in = (NvRmPowerModuleGetMaxFrequency_in *)InBuffer;
+    p_out = (NvRmPowerModuleGetMaxFrequency_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerModuleGetMaxFrequency_params, out) - OFFSET(NvRmPowerModuleGetMaxFrequency_params, inout));
+
+
+    p_out->ret_ = NvRmPowerModuleGetMaxFrequency( p_in->hRmDeviceHandle, p_in->ModuleId );
+
+    return err_;
+}
+
+static NvError NvRmPowerGetPrimaryFrequency_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerGetPrimaryFrequency_in *p_in;
+    NvRmPowerGetPrimaryFrequency_out *p_out;
+
+    p_in = (NvRmPowerGetPrimaryFrequency_in *)InBuffer;
+    p_out = (NvRmPowerGetPrimaryFrequency_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerGetPrimaryFrequency_params, out) - OFFSET(NvRmPowerGetPrimaryFrequency_params, inout));
+
+
+    p_out->ret_ = NvRmPowerGetPrimaryFrequency( p_in->hRmDeviceHandle );
+
+    return err_;
+}
+
+static NvError NvRmPowerGetState_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerGetState_in *p_in;
+    NvRmPowerGetState_out *p_out;
+
+    p_in = (NvRmPowerGetState_in *)InBuffer;
+    p_out = (NvRmPowerGetState_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerGetState_params, out) - OFFSET(NvRmPowerGetState_params, inout));
+
+
+    p_out->ret_ = NvRmPowerGetState( p_in->hRmDeviceHandle, &p_out->pState );
+
+    return err_;
+}
+
+static NvError NvRmPowerEventNotify_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerEventNotify_in *p_in;
+
+    p_in = (NvRmPowerEventNotify_in *)InBuffer;
+
+
+    NvRmPowerEventNotify( p_in->hRmDeviceHandle, p_in->Event );
+
+    return err_;
+}
+
+static NvError NvRmPowerGetEvent_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerGetEvent_in *p_in;
+    NvRmPowerGetEvent_out *p_out;
+
+    p_in = (NvRmPowerGetEvent_in *)InBuffer;
+    p_out = (NvRmPowerGetEvent_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerGetEvent_params, out) - OFFSET(NvRmPowerGetEvent_params, inout));
+
+
+    p_out->ret_ = NvRmPowerGetEvent( p_in->hRmDeviceHandle, p_in->ClientId, &p_out->pEvent );
+
+    return err_;
+}
+
+static NvError NvRmPowerUnRegister_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerUnRegister_in *p_in;
+
+    p_in = (NvRmPowerUnRegister_in *)InBuffer;
+
+
+    NvRmPowerUnRegister( p_in->hRmDeviceHandle, p_in->ClientId );
+
+    return err_;
+}
+
+static NvError NvRmPowerRegister_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerRegister_in *p_in;
+    NvRmPowerRegister_inout *p_inout;
+    NvRmPowerRegister_out *p_out;
+    NvRmPowerRegister_inout inout;
+    NvOsSemaphoreHandle hEventSemaphore = NULL;
+
+    p_in = (NvRmPowerRegister_in *)InBuffer;
+    p_inout = (NvRmPowerRegister_inout *)((NvU8 *)InBuffer + OFFSET(NvRmPowerRegister_params, inout));
+    p_out = (NvRmPowerRegister_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerRegister_params, out) - OFFSET(NvRmPowerRegister_params, inout));
+
+    (void)inout;
+    if( p_in->hEventSemaphore )
+    {
+        err_ = NvOsSemaphoreUnmarshal( p_in->hEventSemaphore, &hEventSemaphore );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+    }
+    inout.pClientId = p_inout->pClientId;
+
+    p_out->ret_ = NvRmPowerRegister( p_in->hRmDeviceHandle, hEventSemaphore, &inout.pClientId );
+
+
+    p_inout = (NvRmPowerRegister_inout *)OutBuffer;
+    p_inout->pClientId = inout.pClientId;
+clean:
+    NvOsSemaphoreDestroy( hEventSemaphore );
+    return err_;
+}
+
+NvError nvrm_power_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_power_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 34:
+        err_ = NvRmKernelPowerResume_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 33:
+        err_ = NvRmKernelPowerSuspend_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 32:
+        err_ = NvRmDfsSetLowVoltageThreshold_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 31:
+        err_ = NvRmDfsGetLowVoltageThreshold_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 30:
+        err_ = NvRmDfsLogBusyGetEntry_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 29:
+        err_ = NvRmDfsLogStarvationGetEntry_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 28:
+        err_ = NvRmDfsLogActivityGetEntry_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 27:
+        err_ = NvRmDfsLogGetMeanFrequencies_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 26:
+        err_ = NvRmDfsLogStart_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 25:
+        err_ = NvRmDfsGetProfileData_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 24:
+        err_ = NvRmDfsSetAvHighCorner_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 23:
+        err_ = NvRmDfsSetCpuEmcHighCorner_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 22:
+        err_ = NvRmDfsSetEmcEnvelope_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 21:
+        err_ = NvRmDfsSetCpuEnvelope_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 20:
+        err_ = NvRmDfsSetTarget_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 19:
+        err_ = NvRmDfsSetLowCorner_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 18:
+        err_ = NvRmDfsSetState_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 17:
+        err_ = NvRmDfsGetClockUtilization_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 16:
+        err_ = NvRmDfsGetState_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 15:
+        err_ = NvRmPowerActivityHint_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 14:
+        err_ = NvRmPowerStarvationHintMulti_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 13:
+        err_ = NvRmPowerStarvationHint_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 12:
+        err_ = NvRmPowerBusyHintMulti_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 11:
+        err_ = NvRmPowerBusyHint_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 10:
+        err_ = NvRmListPowerAwareModules_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 9:
+        err_ = NvRmPowerVoltageControl_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRmPowerModuleClockControl_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmPowerModuleClockConfig_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmPowerModuleGetMaxFrequency_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmPowerGetPrimaryFrequency_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmPowerGetState_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmPowerEventNotify_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmPowerGetEvent_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmPowerUnRegister_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmPowerRegister_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_pwm_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_pwm_dispatch.c
new file mode 100644
index 000000000000..44d1b5e4a3b3
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_pwm_dispatch.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_pwm.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmPwmConfig_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmPwmHandle hPwm;
+    NvRmPwmOutputId OutputId;
+    NvRmPwmMode Mode;
+    NvU32 DutyCycle;
+    NvU32 RequestedFreqHzOrPeriod;
+} NV_ALIGN(4) NvRmPwmConfig_in;
+
+typedef struct NvRmPwmConfig_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPwmConfig_inout;
+
+typedef struct NvRmPwmConfig_out_t
+{
+    NvError ret_;
+    NvU32 pCurrentFreqHzOrPeriod;
+} NV_ALIGN(4) NvRmPwmConfig_out;
+
+typedef struct NvRmPwmConfig_params_t
+{
+    NvRmPwmConfig_in in;
+    NvRmPwmConfig_inout inout;
+    NvRmPwmConfig_out out;
+} NvRmPwmConfig_params;
+
+typedef struct NvRmPwmClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmPwmHandle hPwm;
+} NV_ALIGN(4) NvRmPwmClose_in;
+
+typedef struct NvRmPwmClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPwmClose_inout;
+
+typedef struct NvRmPwmClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPwmClose_out;
+
+typedef struct NvRmPwmClose_params_t
+{
+    NvRmPwmClose_in in;
+    NvRmPwmClose_inout inout;
+    NvRmPwmClose_out out;
+} NvRmPwmClose_params;
+
+typedef struct NvRmPwmOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmPwmOpen_in;
+
+typedef struct NvRmPwmOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPwmOpen_inout;
+
+typedef struct NvRmPwmOpen_out_t
+{
+    NvError ret_;
+    NvRmPwmHandle phPwm;
+} NV_ALIGN(4) NvRmPwmOpen_out;
+
+typedef struct NvRmPwmOpen_params_t
+{
+    NvRmPwmOpen_in in;
+    NvRmPwmOpen_inout inout;
+    NvRmPwmOpen_out out;
+} NvRmPwmOpen_params;
+
+static NvError NvRmPwmConfig_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPwmConfig_in *p_in;
+    NvRmPwmConfig_out *p_out;
+
+    p_in = (NvRmPwmConfig_in *)InBuffer;
+    p_out = (NvRmPwmConfig_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPwmConfig_params, out) - OFFSET(NvRmPwmConfig_params, inout));
+
+
+    p_out->ret_ = NvRmPwmConfig( p_in->hPwm, p_in->OutputId, p_in->Mode, p_in->DutyCycle, p_in->RequestedFreqHzOrPeriod, &p_out->pCurrentFreqHzOrPeriod );
+
+    return err_;
+}
+
+static NvError NvRmPwmClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPwmClose_in *p_in;
+
+    p_in = (NvRmPwmClose_in *)InBuffer;
+
+
+    NvRmPwmClose( p_in->hPwm );
+
+    return err_;
+}
+
+static NvError NvRmPwmOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPwmOpen_in *p_in;
+    NvRmPwmOpen_out *p_out;
+
+    p_in = (NvRmPwmOpen_in *)InBuffer;
+    p_out = (NvRmPwmOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPwmOpen_params, out) - OFFSET(NvRmPwmOpen_params, inout));
+
+
+    p_out->ret_ = NvRmPwmOpen( p_in->hDevice, &p_out->phPwm );
+
+    return err_;
+}
+
+NvError nvrm_pwm_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pwm_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 2:
+        err_ = NvRmPwmConfig_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmPwmClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmPwmOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_spi_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_spi_dispatch.c
new file mode 100644
index 000000000000..8581343518f5
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_spi_dispatch.c
@@ -0,0 +1,407 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_spi.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmSpiSetSignalMode_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmSpiHandle hRmSpi;
+    NvU32 ChipSelectId;
+    NvU32 SpiSignalMode;
+} NV_ALIGN(4) NvRmSpiSetSignalMode_in;
+
+typedef struct NvRmSpiSetSignalMode_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiSetSignalMode_inout;
+
+typedef struct NvRmSpiSetSignalMode_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiSetSignalMode_out;
+
+typedef struct NvRmSpiSetSignalMode_params_t
+{
+    NvRmSpiSetSignalMode_in in;
+    NvRmSpiSetSignalMode_inout inout;
+    NvRmSpiSetSignalMode_out out;
+} NvRmSpiSetSignalMode_params;
+
+typedef struct NvRmSpiGetTransactionData_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmSpiHandle hRmSpi;
+    NvU8  * pReadBuffer;
+    NvU32 BytesRequested;
+    NvU32 WaitTimeout;
+} NV_ALIGN(4) NvRmSpiGetTransactionData_in;
+
+typedef struct NvRmSpiGetTransactionData_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiGetTransactionData_inout;
+
+typedef struct NvRmSpiGetTransactionData_out_t
+{
+    NvError ret_;
+    NvU32 pBytesTransfererd;
+} NV_ALIGN(4) NvRmSpiGetTransactionData_out;
+
+typedef struct NvRmSpiGetTransactionData_params_t
+{
+    NvRmSpiGetTransactionData_in in;
+    NvRmSpiGetTransactionData_inout inout;
+    NvRmSpiGetTransactionData_out out;
+} NvRmSpiGetTransactionData_params;
+
+typedef struct NvRmSpiStartTransaction_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmSpiHandle hRmSpi;
+    NvU32 ChipSelectId;
+    NvU32 ClockSpeedInKHz;
+    NvBool IsReadTransfer;
+    NvU8  * pWriteBuffer;
+    NvU32 BytesRequested;
+    NvU32 PacketSizeInBits;
+} NV_ALIGN(4) NvRmSpiStartTransaction_in;
+
+typedef struct NvRmSpiStartTransaction_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiStartTransaction_inout;
+
+typedef struct NvRmSpiStartTransaction_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmSpiStartTransaction_out;
+
+typedef struct NvRmSpiStartTransaction_params_t
+{
+    NvRmSpiStartTransaction_in in;
+    NvRmSpiStartTransaction_inout inout;
+    NvRmSpiStartTransaction_out out;
+} NvRmSpiStartTransaction_params;
+
+typedef struct NvRmSpiTransaction_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmSpiHandle hRmSpi;
+    NvU32 SpiPinMap;
+    NvU32 ChipSelectId;
+    NvU32 ClockSpeedInKHz;
+    NvU8  * pReadBuffer;
+    NvU8  * pWriteBuffer;
+    NvU32 BytesRequested;
+    NvU32 PacketSizeInBits;
+} NV_ALIGN(4) NvRmSpiTransaction_in;
+
+typedef struct NvRmSpiTransaction_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiTransaction_inout;
+
+typedef struct NvRmSpiTransaction_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiTransaction_out;
+
+typedef struct NvRmSpiTransaction_params_t
+{
+    NvRmSpiTransaction_in in;
+    NvRmSpiTransaction_inout inout;
+    NvRmSpiTransaction_out out;
+} NvRmSpiTransaction_params;
+
+typedef struct NvRmSpiClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmSpiHandle hRmSpi;
+} NV_ALIGN(4) NvRmSpiClose_in;
+
+typedef struct NvRmSpiClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiClose_inout;
+
+typedef struct NvRmSpiClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiClose_out;
+
+typedef struct NvRmSpiClose_params_t
+{
+    NvRmSpiClose_in in;
+    NvRmSpiClose_inout inout;
+    NvRmSpiClose_out out;
+} NvRmSpiClose_params;
+
+typedef struct NvRmSpiOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvU32 IoModule;
+    NvU32 InstanceId;
+    NvBool IsMasterMode;
+} NV_ALIGN(4) NvRmSpiOpen_in;
+
+typedef struct NvRmSpiOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiOpen_inout;
+
+typedef struct NvRmSpiOpen_out_t
+{
+    NvError ret_;
+    NvRmSpiHandle phRmSpi;
+} NV_ALIGN(4) NvRmSpiOpen_out;
+
+typedef struct NvRmSpiOpen_params_t
+{
+    NvRmSpiOpen_in in;
+    NvRmSpiOpen_inout inout;
+    NvRmSpiOpen_out out;
+} NvRmSpiOpen_params;
+
+static NvError NvRmSpiSetSignalMode_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiSetSignalMode_in *p_in;
+
+    p_in = (NvRmSpiSetSignalMode_in *)InBuffer;
+
+
+    NvRmSpiSetSignalMode( p_in->hRmSpi, p_in->ChipSelectId, p_in->SpiSignalMode );
+
+    return err_;
+}
+
+static NvError NvRmSpiGetTransactionData_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiGetTransactionData_in *p_in;
+    NvRmSpiGetTransactionData_out *p_out;
+    NvU8  *pReadBuffer = NULL;
+
+    p_in = (NvRmSpiGetTransactionData_in *)InBuffer;
+    p_out = (NvRmSpiGetTransactionData_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSpiGetTransactionData_params, out) - OFFSET(NvRmSpiGetTransactionData_params, inout));
+
+    if( p_in->BytesRequested && p_in->pReadBuffer )
+    {
+        pReadBuffer = (NvU8  *)NvOsAlloc( p_in->BytesRequested * sizeof( NvU8  ) );
+        if( !pReadBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmSpiGetTransactionData( p_in->hRmSpi, pReadBuffer, p_in->BytesRequested, &p_out->pBytesTransfererd, p_in->WaitTimeout );
+
+    if(p_in->pReadBuffer && pReadBuffer)
+    {
+        err_ = NvOsCopyOut( p_in->pReadBuffer, pReadBuffer, p_in->BytesRequested * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pReadBuffer );
+    return err_;
+}
+
+static NvError NvRmSpiStartTransaction_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiStartTransaction_in *p_in;
+    NvRmSpiStartTransaction_out *p_out;
+    NvU8  *pWriteBuffer = NULL;
+
+    p_in = (NvRmSpiStartTransaction_in *)InBuffer;
+    p_out = (NvRmSpiStartTransaction_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSpiStartTransaction_params, out) - OFFSET(NvRmSpiStartTransaction_params, inout));
+
+    if( p_in->BytesRequested && p_in->pWriteBuffer )
+    {
+        pWriteBuffer = (NvU8  *)NvOsAlloc( p_in->BytesRequested * sizeof( NvU8  ) );
+        if( !pWriteBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pWriteBuffer )
+        {
+            err_ = NvOsCopyIn( pWriteBuffer, p_in->pWriteBuffer, p_in->BytesRequested * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmSpiStartTransaction( p_in->hRmSpi, p_in->ChipSelectId, p_in->ClockSpeedInKHz, p_in->IsReadTransfer, pWriteBuffer, p_in->BytesRequested, p_in->PacketSizeInBits );
+
+clean:
+    NvOsFree( pWriteBuffer );
+    return err_;
+}
+
+static NvError NvRmSpiTransaction_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiTransaction_in *p_in;
+    NvU8  *pReadBuffer = NULL;
+    NvU8  *pWriteBuffer = NULL;
+
+    p_in = (NvRmSpiTransaction_in *)InBuffer;
+
+    if( p_in->BytesRequested && p_in->pReadBuffer )
+    {
+        pReadBuffer = (NvU8  *)NvOsAlloc( p_in->BytesRequested * sizeof( NvU8  ) );
+        if( !pReadBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+    if( p_in->BytesRequested && p_in->pWriteBuffer )
+    {
+        pWriteBuffer = (NvU8  *)NvOsAlloc( p_in->BytesRequested * sizeof( NvU8  ) );
+        if( !pWriteBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pWriteBuffer )
+        {
+            err_ = NvOsCopyIn( pWriteBuffer, p_in->pWriteBuffer, p_in->BytesRequested * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRmSpiTransaction( p_in->hRmSpi, p_in->SpiPinMap, p_in->ChipSelectId, p_in->ClockSpeedInKHz, pReadBuffer, pWriteBuffer, p_in->BytesRequested, p_in->PacketSizeInBits );
+
+    if(p_in->pReadBuffer && pReadBuffer)
+    {
+        err_ = NvOsCopyOut( p_in->pReadBuffer, pReadBuffer, p_in->BytesRequested * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pReadBuffer );
+    NvOsFree( pWriteBuffer );
+    return err_;
+}
+
+static NvError NvRmSpiClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiClose_in *p_in;
+
+    p_in = (NvRmSpiClose_in *)InBuffer;
+
+
+    NvRmSpiClose( p_in->hRmSpi );
+
+    return err_;
+}
+
+static NvError NvRmSpiOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiOpen_in *p_in;
+    NvRmSpiOpen_out *p_out;
+
+    p_in = (NvRmSpiOpen_in *)InBuffer;
+    p_out = (NvRmSpiOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSpiOpen_params, out) - OFFSET(NvRmSpiOpen_params, inout));
+
+
+    p_out->ret_ = NvRmSpiOpen( p_in->hRmDevice, p_in->IoModule, p_in->InstanceId, p_in->IsMasterMode, &p_out->phRmSpi );
+
+    return err_;
+}
+
+NvError nvrm_spi_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_spi_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 5:
+        err_ = NvRmSpiSetSignalMode_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmSpiGetTransactionData_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmSpiStartTransaction_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmSpiTransaction_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmSpiClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmSpiOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_transport_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_transport_dispatch.c
new file mode 100644
index 000000000000..d3da88180177
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_transport_dispatch.c
@@ -0,0 +1,678 @@
+
+#define NV_IDL_IS_DISPATCH
+
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_transport.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+#define MAX_MESSAGE_LENGTH 256
+#define MAX_PORT_NAME_LENGTH 20
+
+typedef struct NvRmTransportRecvMsg_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    void* pMessageBuffer;
+    NvU32 MaxSize;
+} NV_ALIGN(4) NvRmTransportRecvMsg_in;
+
+typedef struct NvRmTransportRecvMsg_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportRecvMsg_inout;
+
+typedef struct NvRmTransportRecvMsg_out_t
+{
+    NvError ret_;
+    NvU32 pMessageSize;
+} NV_ALIGN(4) NvRmTransportRecvMsg_out;
+
+typedef struct NvRmTransportRecvMsg_params_t
+{
+    NvRmTransportRecvMsg_in in;
+    NvRmTransportRecvMsg_inout inout;
+    NvRmTransportRecvMsg_out out;
+} NvRmTransportRecvMsg_params;
+
+typedef struct NvRmTransportSendMsgInLP0_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hPort;
+    void* message;
+    NvU32 MessageSize;
+} NV_ALIGN(4) NvRmTransportSendMsgInLP0_in;
+
+typedef struct NvRmTransportSendMsgInLP0_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportSendMsgInLP0_inout;
+
+typedef struct NvRmTransportSendMsgInLP0_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportSendMsgInLP0_out;
+
+typedef struct NvRmTransportSendMsgInLP0_params_t
+{
+    NvRmTransportSendMsgInLP0_in in;
+    NvRmTransportSendMsgInLP0_inout inout;
+    NvRmTransportSendMsgInLP0_out out;
+} NvRmTransportSendMsgInLP0_params;
+
+typedef struct NvRmTransportSendMsg_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    void* pMessageBuffer;
+    NvU32 MessageSize;
+    NvU32 TimeoutMS;
+} NV_ALIGN(4) NvRmTransportSendMsg_in;
+
+typedef struct NvRmTransportSendMsg_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportSendMsg_inout;
+
+typedef struct NvRmTransportSendMsg_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportSendMsg_out;
+
+typedef struct NvRmTransportSendMsg_params_t
+{
+    NvRmTransportSendMsg_in in;
+    NvRmTransportSendMsg_inout inout;
+    NvRmTransportSendMsg_out out;
+} NvRmTransportSendMsg_params;
+
+typedef struct NvRmTransportSetQueueDepth_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    NvU32 MaxQueueDepth;
+    NvU32 MaxMessageSize;
+} NV_ALIGN(4) NvRmTransportSetQueueDepth_in;
+
+typedef struct NvRmTransportSetQueueDepth_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportSetQueueDepth_inout;
+
+typedef struct NvRmTransportSetQueueDepth_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportSetQueueDepth_out;
+
+typedef struct NvRmTransportSetQueueDepth_params_t
+{
+    NvRmTransportSetQueueDepth_in in;
+    NvRmTransportSetQueueDepth_inout inout;
+    NvRmTransportSetQueueDepth_out out;
+} NvRmTransportSetQueueDepth_params;
+
+typedef struct NvRmTransportConnect_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    NvU32 TimeoutMS;
+} NV_ALIGN(4) NvRmTransportConnect_in;
+
+typedef struct NvRmTransportConnect_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportConnect_inout;
+
+typedef struct NvRmTransportConnect_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportConnect_out;
+
+typedef struct NvRmTransportConnect_params_t
+{
+    NvRmTransportConnect_in in;
+    NvRmTransportConnect_inout inout;
+    NvRmTransportConnect_out out;
+} NvRmTransportConnect_params;
+
+typedef struct NvRmTransportWaitForConnect_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    NvU32 TimeoutMS;
+} NV_ALIGN(4) NvRmTransportWaitForConnect_in;
+
+typedef struct NvRmTransportWaitForConnect_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportWaitForConnect_inout;
+
+typedef struct NvRmTransportWaitForConnect_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportWaitForConnect_out;
+
+typedef struct NvRmTransportWaitForConnect_params_t
+{
+    NvRmTransportWaitForConnect_in in;
+    NvRmTransportWaitForConnect_inout inout;
+    NvRmTransportWaitForConnect_out out;
+} NvRmTransportWaitForConnect_params;
+
+typedef struct NvRmTransportDeInit_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmTransportDeInit_in;
+
+typedef struct NvRmTransportDeInit_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportDeInit_inout;
+
+typedef struct NvRmTransportDeInit_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportDeInit_out;
+
+typedef struct NvRmTransportDeInit_params_t
+{
+    NvRmTransportDeInit_in in;
+    NvRmTransportDeInit_inout inout;
+    NvRmTransportDeInit_out out;
+} NvRmTransportDeInit_params;
+
+typedef struct NvRmTransportInit_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmTransportInit_in;
+
+typedef struct NvRmTransportInit_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportInit_inout;
+
+typedef struct NvRmTransportInit_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportInit_out;
+
+typedef struct NvRmTransportInit_params_t
+{
+    NvRmTransportInit_in in;
+    NvRmTransportInit_inout inout;
+    NvRmTransportInit_out out;
+} NvRmTransportInit_params;
+
+typedef struct NvRmTransportClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+} NV_ALIGN(4) NvRmTransportClose_in;
+
+typedef struct NvRmTransportClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportClose_inout;
+
+typedef struct NvRmTransportClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportClose_out;
+
+typedef struct NvRmTransportClose_params_t
+{
+    NvRmTransportClose_in in;
+    NvRmTransportClose_inout inout;
+    NvRmTransportClose_out out;
+} NvRmTransportClose_params;
+
+typedef struct NvRmTransportGetPortName_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    NvU8  * PortName;
+    NvU32 PortNameSize;
+} NV_ALIGN(4) NvRmTransportGetPortName_in;
+
+typedef struct NvRmTransportGetPortName_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportGetPortName_inout;
+
+typedef struct NvRmTransportGetPortName_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportGetPortName_out;
+
+typedef struct NvRmTransportGetPortName_params_t
+{
+    NvRmTransportGetPortName_in in;
+    NvRmTransportGetPortName_inout inout;
+    NvRmTransportGetPortName_out out;
+} NvRmTransportGetPortName_params;
+
+typedef struct NvRmTransportOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    char * pPortName_data;
+    NvU32 pPortName_len;
+    NvOsSemaphoreHandle RecvMessageSemaphore;
+} NV_ALIGN(4) NvRmTransportOpen_in;
+
+typedef struct NvRmTransportOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportOpen_inout;
+
+typedef struct NvRmTransportOpen_out_t
+{
+    NvError ret_;
+    NvRmTransportHandle phTransport;
+} NV_ALIGN(4) NvRmTransportOpen_out;
+
+typedef struct NvRmTransportOpen_params_t
+{
+    NvRmTransportOpen_in in;
+    NvRmTransportOpen_inout inout;
+    NvRmTransportOpen_out out;
+} NvRmTransportOpen_params;
+
+static NvError NvRmTransportRecvMsg_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportRecvMsg_in *p_in;
+    NvRmTransportRecvMsg_out *p_out;
+    void*  pMessageBuffer = NULL;
+    NvU32 MsgBuff[MAX_MESSAGE_LENGTH/sizeof(NvU32)];
+
+    p_in = (NvRmTransportRecvMsg_in *)InBuffer;
+    p_out = (NvRmTransportRecvMsg_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportRecvMsg_params, out) - OFFSET(NvRmTransportRecvMsg_params, inout));
+
+    if( p_in->MaxSize && p_in->pMessageBuffer )
+    {
+        pMessageBuffer = (void*  )MsgBuff;
+        if( p_in->MaxSize > MAX_MESSAGE_LENGTH )
+            pMessageBuffer = (void* )NvOsAlloc( p_in->MaxSize );
+        if( !pMessageBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmTransportRecvMsg( p_in->hTransport, pMessageBuffer, p_in->MaxSize, &p_out->pMessageSize );
+
+    if(p_in->pMessageBuffer && pMessageBuffer)
+    {
+        err_ = NvOsCopyOut( p_in->pMessageBuffer, pMessageBuffer, p_in->MaxSize );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    if (pMessageBuffer != MsgBuff)
+        NvOsFree( pMessageBuffer );
+    return err_;
+}
+
+static NvError NvRmTransportSendMsgInLP0_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportSendMsgInLP0_in *p_in;
+    NvRmTransportSendMsgInLP0_out *p_out;
+    void*  message = NULL;
+    NvU32 MsgBuff[MAX_MESSAGE_LENGTH/sizeof(NvU32)];
+
+    p_in = (NvRmTransportSendMsgInLP0_in *)InBuffer;
+    p_out = (NvRmTransportSendMsgInLP0_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportSendMsgInLP0_params, out) - OFFSET(NvRmTransportSendMsgInLP0_params, inout));
+
+    if( p_in->MessageSize && p_in->message )
+    {
+        message = (void*  )MsgBuff;
+        if( p_in->MessageSize > MAX_MESSAGE_LENGTH )
+            message = (void*  )NvOsAlloc( p_in->MessageSize );
+        if( !message )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->message )
+        {
+            err_ = NvOsCopyIn( message, p_in->message, p_in->MessageSize );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmTransportSendMsgInLP0( p_in->hPort, message, p_in->MessageSize );
+
+clean:
+    if( message != MsgBuff )
+        NvOsFree( message );
+    return err_;
+}
+
+static NvError NvRmTransportSendMsg_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportSendMsg_in *p_in;
+    NvRmTransportSendMsg_out *p_out;
+    void*  pMessageBuffer = NULL;
+    NvU32 MsgBuff[MAX_MESSAGE_LENGTH/sizeof(NvU32)];
+
+    p_in = (NvRmTransportSendMsg_in *)InBuffer;
+    p_out = (NvRmTransportSendMsg_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportSendMsg_params, out) - OFFSET(NvRmTransportSendMsg_params, inout));
+
+    if( p_in->MessageSize && p_in->pMessageBuffer )
+    {
+        pMessageBuffer = (void*  )&MsgBuff[0];
+        if( p_in->MessageSize > MAX_MESSAGE_LENGTH )
+            pMessageBuffer = (void*  )NvOsAlloc( p_in->MessageSize );
+        if( !pMessageBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pMessageBuffer )
+        {
+            err_ = NvOsCopyIn( pMessageBuffer, p_in->pMessageBuffer, p_in->MessageSize );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmTransportSendMsg( p_in->hTransport, pMessageBuffer, p_in->MessageSize, p_in->TimeoutMS );
+
+clean:
+    if( pMessageBuffer != MsgBuff )
+        NvOsFree( pMessageBuffer );
+    return err_;
+}
+
+static NvError NvRmTransportSetQueueDepth_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportSetQueueDepth_in *p_in;
+    NvRmTransportSetQueueDepth_out *p_out;
+
+    p_in = (NvRmTransportSetQueueDepth_in *)InBuffer;
+    p_out = (NvRmTransportSetQueueDepth_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportSetQueueDepth_params, out) - OFFSET(NvRmTransportSetQueueDepth_params, inout));
+
+
+    p_out->ret_ = NvRmTransportSetQueueDepth( p_in->hTransport, p_in->MaxQueueDepth, p_in->MaxMessageSize );
+
+    return err_;
+}
+
+static NvError NvRmTransportConnect_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportConnect_in *p_in;
+    NvRmTransportConnect_out *p_out;
+
+    p_in = (NvRmTransportConnect_in *)InBuffer;
+    p_out = (NvRmTransportConnect_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportConnect_params, out) - OFFSET(NvRmTransportConnect_params, inout));
+
+
+    p_out->ret_ = NvRmTransportConnect( p_in->hTransport, p_in->TimeoutMS );
+
+    return err_;
+}
+
+static NvError NvRmTransportWaitForConnect_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportWaitForConnect_in *p_in;
+    NvRmTransportWaitForConnect_out *p_out;
+
+    p_in = (NvRmTransportWaitForConnect_in *)InBuffer;
+    p_out = (NvRmTransportWaitForConnect_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportWaitForConnect_params, out) - OFFSET(NvRmTransportWaitForConnect_params, inout));
+
+
+    p_out->ret_ = NvRmTransportWaitForConnect( p_in->hTransport, p_in->TimeoutMS );
+
+    return err_;
+}
+
+static NvError NvRmTransportDeInit_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportDeInit_in *p_in;
+
+    p_in = (NvRmTransportDeInit_in *)InBuffer;
+
+
+    NvRmTransportDeInit( p_in->hRmDevice );
+
+    return err_;
+}
+
+static NvError NvRmTransportInit_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportInit_in *p_in;
+    NvRmTransportInit_out *p_out;
+
+    p_in = (NvRmTransportInit_in *)InBuffer;
+    p_out = (NvRmTransportInit_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportInit_params, out) - OFFSET(NvRmTransportInit_params, inout));
+
+
+    p_out->ret_ = NvRmTransportInit( p_in->hRmDevice );
+
+    return err_;
+}
+
+static NvError NvRmTransportClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportClose_in *p_in;
+
+    p_in = (NvRmTransportClose_in *)InBuffer;
+
+
+    NvRmTransportClose( p_in->hTransport );
+
+    return err_;
+}
+
+static NvError NvRmTransportGetPortName_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportGetPortName_in *p_in;
+    NvU8  *PortName = NULL;
+    NvU32 PortNameBuff[MAX_PORT_NAME_LENGTH/sizeof(NvU32)];
+
+    p_in = (NvRmTransportGetPortName_in *)InBuffer;
+
+    if( p_in->PortNameSize && p_in->PortName )
+    {
+        PortName = (NvU8  *)PortNameBuff;
+        if( (p_in->PortNameSize * sizeof(NvU8)) > MAX_PORT_NAME_LENGTH )
+            PortName = (NvU8  *)NvOsAlloc( p_in->PortNameSize * sizeof( NvU8  ) );
+        if( !PortName )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->PortName )
+        {
+            err_ = NvOsCopyIn( PortName, p_in->PortName, p_in->PortNameSize * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRmTransportGetPortName( p_in->hTransport, PortName, p_in->PortNameSize );
+
+    if(p_in->PortName && PortName)
+    {
+        err_ = NvOsCopyOut( p_in->PortName, PortName, p_in->PortNameSize * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    if ( PortName != (NvU8  *)PortNameBuff )
+        NvOsFree( PortName );
+    return err_;
+}
+
+static NvError NvRmTransportOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportOpen_in *p_in;
+    NvRmTransportOpen_out *p_out;
+    char *pPortName = NULL;
+    NvOsSemaphoreHandle RecvMessageSemaphore = NULL;
+    NvU32 PortNameBuff[MAX_PORT_NAME_LENGTH/sizeof(NvU32)];
+
+    p_in = (NvRmTransportOpen_in *)InBuffer;
+    p_out = (NvRmTransportOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportOpen_params, out) - OFFSET(NvRmTransportOpen_params, inout));
+
+    if( p_in->pPortName_len )
+    {
+        pPortName = (char *)PortNameBuff;
+        if( p_in->pPortName_len > MAX_PORT_NAME_LENGTH )
+            pPortName = NvOsAlloc( p_in->pPortName_len );
+        if( !pPortName )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        err_ = NvOsCopyIn( pPortName, p_in->pPortName_data, p_in->pPortName_len );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+        if( pPortName[p_in->pPortName_len - 1] != 0 )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+    }
+    if( p_in->RecvMessageSemaphore )
+    {
+        err_ = NvOsSemaphoreUnmarshal( p_in->RecvMessageSemaphore, &RecvMessageSemaphore );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmTransportOpen( p_in->hRmDevice, pPortName, RecvMessageSemaphore, &p_out->phTransport );
+
+clean:
+    if( pPortName != (char *)PortNameBuff )
+        NvOsFree( pPortName );
+    NvOsSemaphoreDestroy( RecvMessageSemaphore );
+    return err_;
+}
+
+NvError nvrm_transport_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_transport_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 10:
+        err_ = NvRmTransportRecvMsg_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 9:
+        err_ = NvRmTransportSendMsgInLP0_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRmTransportSendMsg_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmTransportSetQueueDepth_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmTransportConnect_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmTransportWaitForConnect_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmTransportDeInit_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmTransportInit_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmTransportClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmTransportGetPortName_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmTransportOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nvrm/dispatch/nvrm_xpc_dispatch.c b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_xpc_dispatch.c
new file mode 100644
index 000000000000..16b98ede32e0
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/dispatch/nvrm_xpc_dispatch.c
@@ -0,0 +1,348 @@
+
+#define NV_IDL_IS_DISPATCH
+
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_xpc.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmXpcModuleRelease_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmModuleID modId;
+} NV_ALIGN(4) NvRmXpcModuleRelease_in;
+
+typedef struct NvRmXpcModuleRelease_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmXpcModuleRelease_inout;
+
+typedef struct NvRmXpcModuleRelease_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmXpcModuleRelease_out;
+
+typedef struct NvRmXpcModuleRelease_params_t
+{
+    NvRmXpcModuleRelease_in in;
+    NvRmXpcModuleRelease_inout inout;
+    NvRmXpcModuleRelease_out out;
+} NvRmXpcModuleRelease_params;
+
+typedef struct NvRmXpcModuleAcquire_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmModuleID modId;
+} NV_ALIGN(4) NvRmXpcModuleAcquire_in;
+
+typedef struct NvRmXpcModuleAcquire_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmXpcModuleAcquire_inout;
+
+typedef struct NvRmXpcModuleAcquire_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmXpcModuleAcquire_out;
+
+typedef struct NvRmXpcModuleAcquire_params_t
+{
+    NvRmXpcModuleAcquire_in in;
+    NvRmXpcModuleAcquire_inout inout;
+    NvRmXpcModuleAcquire_out out;
+} NvRmXpcModuleAcquire_params;
+
+typedef struct NvRmXpcInitArbSemaSystem_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmXpcInitArbSemaSystem_in;
+
+typedef struct NvRmXpcInitArbSemaSystem_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmXpcInitArbSemaSystem_inout;
+
+typedef struct NvRmXpcInitArbSemaSystem_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmXpcInitArbSemaSystem_out;
+
+typedef struct NvRmXpcInitArbSemaSystem_params_t
+{
+    NvRmXpcInitArbSemaSystem_in in;
+    NvRmXpcInitArbSemaSystem_inout inout;
+    NvRmXpcInitArbSemaSystem_out out;
+} NvRmXpcInitArbSemaSystem_params;
+
+typedef struct NvRmPrivXpcGetMessage_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmPrivXpcMessageHandle hXpcMessage;
+} NV_ALIGN(4) NvRmPrivXpcGetMessage_in;
+
+typedef struct NvRmPrivXpcGetMessage_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPrivXpcGetMessage_inout;
+
+typedef struct NvRmPrivXpcGetMessage_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmPrivXpcGetMessage_out;
+
+typedef struct NvRmPrivXpcGetMessage_params_t
+{
+    NvRmPrivXpcGetMessage_in in;
+    NvRmPrivXpcGetMessage_inout inout;
+    NvRmPrivXpcGetMessage_out out;
+} NvRmPrivXpcGetMessage_params;
+
+typedef struct NvRmPrivXpcSendMessage_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmPrivXpcMessageHandle hXpcMessage;
+    NvU32 data;
+} NV_ALIGN(4) NvRmPrivXpcSendMessage_in;
+
+typedef struct NvRmPrivXpcSendMessage_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPrivXpcSendMessage_inout;
+
+typedef struct NvRmPrivXpcSendMessage_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmPrivXpcSendMessage_out;
+
+typedef struct NvRmPrivXpcSendMessage_params_t
+{
+    NvRmPrivXpcSendMessage_in in;
+    NvRmPrivXpcSendMessage_inout inout;
+    NvRmPrivXpcSendMessage_out out;
+} NvRmPrivXpcSendMessage_params;
+
+typedef struct NvRmPrivXpcDestroy_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmPrivXpcMessageHandle hXpcMessage;
+} NV_ALIGN(4) NvRmPrivXpcDestroy_in;
+
+typedef struct NvRmPrivXpcDestroy_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPrivXpcDestroy_inout;
+
+typedef struct NvRmPrivXpcDestroy_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPrivXpcDestroy_out;
+
+typedef struct NvRmPrivXpcDestroy_params_t
+{
+    NvRmPrivXpcDestroy_in in;
+    NvRmPrivXpcDestroy_inout inout;
+    NvRmPrivXpcDestroy_out out;
+} NvRmPrivXpcDestroy_params;
+
+typedef struct NvRmPrivXpcCreate_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmPrivXpcCreate_in;
+
+typedef struct NvRmPrivXpcCreate_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPrivXpcCreate_inout;
+
+typedef struct NvRmPrivXpcCreate_out_t
+{
+    NvError ret_;
+    NvRmPrivXpcMessageHandle phXpcMessage;
+} NV_ALIGN(4) NvRmPrivXpcCreate_out;
+
+typedef struct NvRmPrivXpcCreate_params_t
+{
+    NvRmPrivXpcCreate_in in;
+    NvRmPrivXpcCreate_inout inout;
+    NvRmPrivXpcCreate_out out;
+} NvRmPrivXpcCreate_params;
+
+static NvError NvRmXpcModuleRelease_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmXpcModuleRelease_in *p_in;
+
+    p_in = (NvRmXpcModuleRelease_in *)InBuffer;
+
+
+    NvRmXpcModuleRelease( p_in->modId );
+
+    return err_;
+}
+
+static NvError NvRmXpcModuleAcquire_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmXpcModuleAcquire_in *p_in;
+
+    p_in = (NvRmXpcModuleAcquire_in *)InBuffer;
+
+
+    NvRmXpcModuleAcquire( p_in->modId );
+
+    return err_;
+}
+
+static NvError NvRmXpcInitArbSemaSystem_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmXpcInitArbSemaSystem_in *p_in;
+    NvRmXpcInitArbSemaSystem_out *p_out;
+
+    p_in = (NvRmXpcInitArbSemaSystem_in *)InBuffer;
+    p_out = (NvRmXpcInitArbSemaSystem_out *)((NvU8 *)OutBuffer + OFFSET(NvRmXpcInitArbSemaSystem_params, out) - OFFSET(NvRmXpcInitArbSemaSystem_params, inout));
+
+
+    p_out->ret_ = NvRmXpcInitArbSemaSystem( p_in->hDevice );
+
+    return err_;
+}
+
+static NvError NvRmPrivXpcGetMessage_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPrivXpcGetMessage_in *p_in;
+    NvRmPrivXpcGetMessage_out *p_out;
+
+    p_in = (NvRmPrivXpcGetMessage_in *)InBuffer;
+    p_out = (NvRmPrivXpcGetMessage_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPrivXpcGetMessage_params, out) - OFFSET(NvRmPrivXpcGetMessage_params, inout));
+
+
+    p_out->ret_ = NvRmPrivXpcGetMessage( p_in->hXpcMessage );
+
+    return err_;
+}
+
+static NvError NvRmPrivXpcSendMessage_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPrivXpcSendMessage_in *p_in;
+    NvRmPrivXpcSendMessage_out *p_out;
+
+    p_in = (NvRmPrivXpcSendMessage_in *)InBuffer;
+    p_out = (NvRmPrivXpcSendMessage_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPrivXpcSendMessage_params, out) - OFFSET(NvRmPrivXpcSendMessage_params, inout));
+
+
+    p_out->ret_ = NvRmPrivXpcSendMessage( p_in->hXpcMessage, p_in->data );
+
+    return err_;
+}
+
+static NvError NvRmPrivXpcDestroy_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPrivXpcDestroy_in *p_in;
+
+    p_in = (NvRmPrivXpcDestroy_in *)InBuffer;
+
+
+    NvRmPrivXpcDestroy( p_in->hXpcMessage );
+
+    return err_;
+}
+
+static NvError NvRmPrivXpcCreate_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPrivXpcCreate_in *p_in;
+    NvRmPrivXpcCreate_out *p_out;
+
+    p_in = (NvRmPrivXpcCreate_in *)InBuffer;
+    p_out = (NvRmPrivXpcCreate_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPrivXpcCreate_params, out) - OFFSET(NvRmPrivXpcCreate_params, inout));
+
+
+    p_out->ret_ = NvRmPrivXpcCreate( p_in->hDevice, &p_out->phXpcMessage );
+
+    return err_;
+}
+
+NvError nvrm_xpc_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_xpc_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 6:
+        err_ = NvRmXpcModuleRelease_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmXpcModuleAcquire_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmXpcInitArbSemaSystem_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmPrivXpcGetMessage_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmPrivXpcSendMessage_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmPrivXpcDestroy_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmPrivXpcCreate_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}