tegra framebuffer - dsi one shot support

DSI one shot support requires register access in the tegra framebuffer to
poke the frame trigger bit (with both the trigger bit and the tearing effect
signal are high, a frame of pixels will be sent to the panel). The boot args
must also be expanded to have a "use tearing effect" flag.

tegra RM: Expanded Display clock configuration options.

Added an option for restricted Display clock synchronization with MIPI
PLL - select MIPI PLL as a pixel clock source, but preserve PLL settings.
To specify this option flag NvRmClockConfig_InternalClockForPads should
be set by RM client along with NvRmClockConfig_MipiSync flag (in the
absence of the former flag, MIPI PLL can be re-configured at RM discretion
- current behavior).

Change-Id: I495c2d76656efe8653aa5731c07180c2bfcd2fc0
Reviewed-on: http://git-master/r/2342
Tested-by: Arthur Spence <aspence@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

1 files changed, 4 insertions, 2 deletions

diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
index f13ef4797306..ca63729f2673 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
@@ -1106,9 +1106,11 @@ Ap15DisplayClockConfigure(
      */
     if (flags & NvRmClockConfig_MipiSync)
     {
-        // PLLD requested
+        // PLLD requested - use it as a source, and reconfigure,
+        //  unless it is also routed to the pads
         SourceId = NvRmClockSource_PllD0;
-        Ap15PllDConfigure(hRmDevice, TargetFreq);
+        if (!(flags & NvRmClockConfig_InternalClockForPads))
+            Ap15PllDConfigure(hRmDevice, TargetFreq);
     }
     else if (NvRmIsFreqRangeReachable(
         SourceClockFreq, MinFreq, MaxFreq, NVRM_DISPLAY_DIVIDER_MAX))