diff options
| author | Jay Agarwal <jagarwal@nvidia.com> | 2012-02-27 20:19:20 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-03-07 22:14:35 -0800 |
| commit | 65b1807ed71f72a6f3d8d47e70e4f42d9a874518 (patch) | |
| tree | 3ad94d36cecb338d2f3a4c278fd408441620329a /arch/arm/mach-tegra/pcie.c | |
| parent | d4729f6e4ba0416f0f38383cfe440518653cabaa (diff) | |
tegra: pcie: Fix individual port detection on T20
This commit fix two issues.
1. MMIO space should be reserved for T30 as well
2. There is a bug in link reset sequence causing
problem in detecting the other slot as well
on T20
bug 826956
bug 637871
Reviewed-on: http://git-master/r/66814
(cherry picked from commit 11ce98902d0687646eb30a4bd1f9a1d5e8da34ce)
Change-Id: I1843e3a1d897a36768b05b33ab7624889191d011
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/86134
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pcie.c')
| -rw-r--r-- | arch/arm/mach-tegra/pcie.c | 27 |
1 files changed, 11 insertions, 16 deletions
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index e16910cbe93c..462142f88072 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -236,15 +236,9 @@ #define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M) #define MMIO_SIZE SZ_64K #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) -#define MEM_SIZE_0 SZ_128M -#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) -#define MEM_SIZE_1 SZ_128M -#define MEM_SIZE (MEM_SIZE_0 + MEM_SIZE_1) -#define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1) -#define PREFETCH_MEM_SIZE_0 SZ_128M -#define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0) -#define PREFETCH_MEM_SIZE_1 SZ_128M -#define PREFETCH_MEM_SIZE (PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1) +#define MEM_SIZE SZ_256M +#define PREFETCH_MEM_BASE_0 (MEM_BASE_0 + MEM_SIZE) +#define PREFETCH_MEM_SIZE SZ_512M #else @@ -992,6 +986,7 @@ static int __init tegra_pcie_get_resources(void) goto err_map_reg; } res_mmio = &tegra_pcie.res_mmio; + err = request_resource(&iomem_resource, res_mmio); if (err) { pr_err("PCIE: Failed to request resources: %d\n", err); @@ -1045,6 +1040,13 @@ static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx, int timeout; do { + /* Pulse the PEX reset */ + reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST; + afi_writel(reg, reset_reg); + mdelay(1); + reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST; + afi_writel(reg, reset_reg); + timeout = TEGRA_PCIE_LINKUP_TIMEOUT; while (timeout) { reg = readl(pp->base + RP_VEND_XP); @@ -1073,13 +1075,6 @@ static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx, } retry: - /* Pulse the PEX reset */ - reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST; - afi_writel(reg, reset_reg); - mdelay(1); - reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST; - afi_writel(reg, reset_reg); - retries--; } while (retries); |