diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2011-09-14 19:10:53 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:58 -0800 |
| commit | bec3be681c1b4feba7b8f9679952a650d16343da (patch) | |
| tree | 06e6b0331203f03d6109f1320327ea27a2129d90 /arch/arm/mach-tegra/pinmux-t2-tables.c | |
| parent | 6a1523570c5b7425d2b0dfc24dac207e09466720 (diff) | |
Arm: Tegra: Cardhu: Set slew rise/fall rates properly
Setting the slewrise and slewfall rates properly.
Bug 811303
Reviewed-on: http://git-master/r/52367
(cherry picked from commit 337b90b5a359c4f320f58f5026fa511dca5d8031)
Change-Id: I518b4dcdad8ac338cf03d4fb6c634b0747a82836
Reviewed-on: http://git-master/r/62326
(cherry picked from commit 7a04424fb0b8c1f36f28c99f73a313cd192360e9)
Reviewed-on: http://git-master/r/63813
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Racfd777be42f83018a9e295e1c7048ebb02f7f9e
Diffstat (limited to 'arch/arm/mach-tegra/pinmux-t2-tables.c')
| -rw-r--r-- | arch/arm/mach-tegra/pinmux-t2-tables.c | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-t2-tables.c index 86cfdbe7bf0f..3b2b2f4e9cbe 100644 --- a/arch/arm/mach-tegra/pinmux-t2-tables.c +++ b/arch/arm/mach-tegra/pinmux-t2-tables.c @@ -32,14 +32,19 @@ #include <mach/pinmux.h> #include "gpio-names.h" -#define SET_DRIVE_PINGROUP(pg_name, r, drv_down_offset, drv_down_mask, drv_up_offset, drv_up_mask) \ - [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ - .name = #pg_name, \ - .reg = r, \ - .drvup_offset = drv_up_offset, \ - .drvup_mask = drv_up_mask, \ - .drvdown_offset = drv_down_offset, \ - .drvdown_mask = drv_down_mask, \ +#define SET_DRIVE_PINGROUP(pg_name, r, drv_down_offset, drv_down_mask, drv_up_offset, drv_up_mask, \ + slew_rise_offset, slew_rise_mask, slew_fall_offset, slew_fall_mask) \ + [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .reg = r, \ + .drvup_offset = drv_up_offset, \ + .drvup_mask = drv_up_mask, \ + .drvdown_offset = drv_down_offset, \ + .drvdown_mask = drv_down_mask, \ + .slewrise_offset = slew_rise_offset, \ + .slewrise_mask = slew_rise_mask, \ + .slewfall_offset = slew_fall_offset, \ + .slewfall_mask = slew_fall_mask, \ } #define DEFAULT_DRIVE_PINGROUP(pg_name, r) \ @@ -50,6 +55,10 @@ .drvup_mask = 0x1f, \ .drvdown_offset = 12, \ .drvdown_mask = 0x1f, \ + .slewrise_offset = 28, \ + .slewrise_mask = 0x3, \ + .slewfall_offset = 30, \ + .slewfall_mask = 0x3, \ } const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { |