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authorPavan Kunapuli <pkunapuli@nvidia.com>2011-09-14 19:10:53 +0530
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:49:58 -0800
commitbec3be681c1b4feba7b8f9679952a650d16343da (patch)
tree06e6b0331203f03d6109f1320327ea27a2129d90 /arch/arm/mach-tegra/pinmux.c
parent6a1523570c5b7425d2b0dfc24dac207e09466720 (diff)
Arm: Tegra: Cardhu: Set slew rise/fall rates properly
Setting the slewrise and slewfall rates properly. Bug 811303 Reviewed-on: http://git-master/r/52367 (cherry picked from commit 337b90b5a359c4f320f58f5026fa511dca5d8031) Change-Id: I518b4dcdad8ac338cf03d4fb6c634b0747a82836 Reviewed-on: http://git-master/r/62326 (cherry picked from commit 7a04424fb0b8c1f36f28c99f73a313cd192360e9) Reviewed-on: http://git-master/r/63813 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Rebase-Id: Racfd777be42f83018a9e295e1c7048ebb02f7f9e
Diffstat (limited to 'arch/arm/mach-tegra/pinmux.c')
-rw-r--r--arch/arm/mach-tegra/pinmux.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index a9f698b3590f..4b4ced06c15c 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -776,8 +776,9 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
spin_lock_irqsave(&mux_lock, flags);
reg = pg_readl(drive_pingroups[pg].reg);
- reg &= ~(0x3 << 28);
- reg |= slew_rising << 28;
+ reg &= ~(drive_pingroups[pg].slewrise_mask <<
+ drive_pingroups[pg].slewrise_offset);
+ reg |= slew_rising << drive_pingroups[pg].slewrise_offset;
pg_writel(reg, drive_pingroups[pg].reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -799,8 +800,9 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
spin_lock_irqsave(&mux_lock, flags);
reg = pg_readl(drive_pingroups[pg].reg);
- reg &= ~(0x3 << 30);
- reg |= slew_falling << 30;
+ reg &= ~(drive_pingroups[pg].slewfall_mask <<
+ drive_pingroups[pg].slewfall_offset);
+ reg |= slew_falling << drive_pingroups[pg].slewfall_offset;
pg_writel(reg, drive_pingroups[pg].reg);
spin_unlock_irqrestore(&mux_lock, flags);