diff options
author | Harry Hong <hhong@nvidia.com> | 2012-01-30 14:11:16 +0900 |
---|---|---|
committer | Simone Willett <swillett@nvidia.com> | 2012-02-09 12:56:09 -0800 |
commit | 710e291cabb68d047b9098f24baa22556b1e3ec0 (patch) | |
tree | 69ca16afc3ac4ed0f33f3c5fa5168cdf3e2d09e2 /arch/arm/mach-tegra/pinmux.c | |
parent | a519c58529ffcdb2e450a1b65a1bdaf78b419145 (diff) |
ARM: tegra: pinmux: Correct the offset of padcfg reg.
Changed the offset of each controls in pad control register
based on tegra_soc_drive_pingroups array instead of fixed offset
when printing debug info of pinmux drive settings.
bug 929985
Signed-off-by: Harry Hong <hhong@nvidia.com>
Reviewed-on: http://git-master/r/77978
(cherry picked from commit 4a106e10b664837bf8652a7afe49788f5bb07582)
Change-Id: I387b095d09582efdcdc4c374e5fc984a0f3ac2b8
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/80001
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pinmux.c')
-rw-r--r-- | arch/arm/mach-tegra/pinmux.c | 27 |
1 files changed, 16 insertions, 11 deletions
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index bf8627fb2c94..245aa627fdfe 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -28,10 +28,10 @@ #define HSM_EN(reg) (((reg) >> 2) & 0x1) #define SCHMT_EN(reg) (((reg) >> 3) & 0x1) #define LPMD(reg) (((reg) >> 4) & 0x3) -#define DRVDN(reg) (((reg) >> 12) & 0x1f) -#define DRVUP(reg) (((reg) >> 20) & 0x1f) -#define SLWR(reg) (((reg) >> 28) & 0x3) -#define SLWF(reg) (((reg) >> 30) & 0x3) +#define DRVDN(reg, offset) (((reg) >> offset) & 0x1f) +#define DRVUP(reg, offset) (((reg) >> offset) & 0x1f) +#define SLWR(reg, offset) (((reg) >> offset) & 0x3) +#define SLWF(reg, offset) (((reg) >> offset) & 0x3) static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups; static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups; @@ -975,6 +975,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused) { int i; int len; + u8 offset; for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { u32 reg; @@ -1008,19 +1009,23 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused) len = strlen(drive_name(LPMD(reg))); dbg_pad_field(s, 5 - len); - seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg)); - len = DRVDN(reg) < 10 ? 1 : 2; + offset = drive_pingroups[i].drvdown_offset; + seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg, offset)); + len = DRVDN(reg, offset) < 10 ? 1 : 2; dbg_pad_field(s, 2 - len); - seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg)); - len = DRVUP(reg) < 10 ? 1 : 2; + offset = drive_pingroups[i].drvup_offset; + seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg, offset)); + len = DRVUP(reg, offset) < 10 ? 1 : 2; dbg_pad_field(s, 2 - len); - seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg))); - len = strlen(slew_name(SLWR(reg))); + offset = drive_pingroups[i].slewrise_offset; + seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg, offset))); + len = strlen(slew_name(SLWR(reg, offset))); dbg_pad_field(s, 7 - len); - seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg))); + offset= drive_pingroups[i].slewfall_offset; + seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg, offset))); seq_printf(s, "},\n"); } |