diff options
| author | Harry Hong <hhong@nvidia.com> | 2012-01-30 14:11:16 +0900 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-22 23:50:42 -0700 |
| commit | 3bc7e6d6872cbd98179811efad91615b167f2c20 (patch) | |
| tree | 00e3a8ed6107792dee33d5369384e0d0a1b5e171 /arch/arm/mach-tegra/pinmux.c | |
| parent | d08c6c471e7269f2088e9b20c98a848271508f90 (diff) | |
ARM: tegra: pinmux: Correct the offset of padcfg reg.
Changed the offset of each controls in pad control register
based on tegra_soc_drive_pingroups array instead of fixed offset
when printing debug info of pinmux drive settings.
bug 929985
Signed-off-by: Harry Hong <hhong@nvidia.com>
Reviewed-on: http://git-master/r/77978
(cherry picked from commit 4a106e10b664837bf8652a7afe49788f5bb07582)
Change-Id: I387b095d09582efdcdc4c374e5fc984a0f3ac2b8
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/80001
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R6c692dba040132a28f59e2e207c40f83d18e3a50
Diffstat (limited to 'arch/arm/mach-tegra/pinmux.c')
| -rw-r--r-- | arch/arm/mach-tegra/pinmux.c | 27 |
1 files changed, 16 insertions, 11 deletions
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index bb12228b9230..0515b933a755 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -30,10 +30,10 @@ #define HSM_EN(reg) (((reg) >> 2) & 0x1) #define SCHMT_EN(reg) (((reg) >> 3) & 0x1) #define LPMD(reg) (((reg) >> 4) & 0x3) -#define DRVDN(reg) (((reg) >> 12) & 0x1f) -#define DRVUP(reg) (((reg) >> 20) & 0x1f) -#define SLWR(reg) (((reg) >> 28) & 0x3) -#define SLWF(reg) (((reg) >> 30) & 0x3) +#define DRVDN(reg, offset) (((reg) >> offset) & 0x1f) +#define DRVUP(reg, offset) (((reg) >> offset) & 0x1f) +#define SLWR(reg, offset) (((reg) >> offset) & 0x3) +#define SLWF(reg, offset) (((reg) >> offset) & 0x3) static const struct tegra_pingroup_desc *pingroups; static const struct tegra_drive_pingroup_desc *drive_pingroups; @@ -1093,6 +1093,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused) { int i; int len; + u8 offset; for (i = 0; i < drive_max; i++) { u32 reg; @@ -1127,19 +1128,23 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused) len = strlen(drive_name(LPMD(reg))); dbg_pad_field(s, 5 - len); - seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg)); - len = DRVDN(reg) < 10 ? 1 : 2; + offset = drive_pingroups[i].drvdown_offset; + seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg, offset)); + len = DRVDN(reg, offset) < 10 ? 1 : 2; dbg_pad_field(s, 2 - len); - seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg)); - len = DRVUP(reg) < 10 ? 1 : 2; + offset = drive_pingroups[i].drvup_offset; + seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg, offset)); + len = DRVUP(reg, offset) < 10 ? 1 : 2; dbg_pad_field(s, 2 - len); - seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg))); - len = strlen(slew_name(SLWR(reg))); + offset = drive_pingroups[i].slewrise_offset; + seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg, offset))); + len = strlen(slew_name(SLWR(reg, offset))); dbg_pad_field(s, 7 - len); - seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg))); + offset= drive_pingroups[i].slewfall_offset; + seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg, offset))); seq_printf(s, "},\n"); } |