diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2012-10-12 14:38:17 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-10-23 15:17:59 -0700 |
| commit | 5c6353959f2522efc592a662860fb19a37d4a4e6 (patch) | |
| tree | 3ccdee3fb198b3f0d2b10c7708e0ff7db122f811 /arch/arm/mach-tegra/pinmux.c | |
| parent | f509df5f91bb0e6e13d55eb46b15ae2bcdb3a1d9 (diff) | |
ARM: tegra: pinmux: Set drive type for pads
Some of the pads have drive type setting. Added
support for configuring the same.
Updated the correct drive strength offsets and
masks for SDIO1, SDIO3 and GMA pads in T11x
pinmux tables.
Bug 1156152
Reviewed-on: http://git-master/r/144029
(cherry picked from commit 7d328139032484e65be15d0a35b53bd98c9544fb)
Change-Id: Ib3b8a2a79256fc557cfe62403eb1a7c237246275
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/146408
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pinmux.c')
| -rw-r--r-- | arch/arm/mach-tegra/pinmux.c | 38 |
1 files changed, 36 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index c7839703b0aa..4eb5f96b4108 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -729,6 +729,32 @@ static int tegra_drive_pinmux_set_slew_falling(int pg, return 0; } +static int tegra_drive_pinmux_set_drive_type(int pg, + enum tegra_drive_type drive_type) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= drive_max) + return -ERANGE; + + if (drive_type < 0 || drive_type >= TEGRA_MAX_DRIVE_TYPE) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + if (drive_pingroups[pg].drvtype_valid) { + reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + reg &= ~(drive_pingroups[pg].drvtype_mask << + drive_pingroups[pg].drvtype_offset); + reg |= drive_type << drive_pingroups[pg].drvtype_offset; + pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); + } + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + static void tegra_drive_pinmux_config_pingroup(int pingroup, enum tegra_hsm hsm, enum tegra_schmitt schmitt, @@ -736,7 +762,8 @@ static void tegra_drive_pinmux_config_pingroup(int pingroup, enum tegra_pull_strength pull_down, enum tegra_pull_strength pull_up, enum tegra_slew slew_rising, - enum tegra_slew slew_falling) + enum tegra_slew slew_falling, + enum tegra_drive_type drive_type) { int err; @@ -781,6 +808,12 @@ static void tegra_drive_pinmux_config_pingroup(int pingroup, pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n", drive_pinmux_name(pingroup), slew_name(slew_falling), err); + + err = tegra_drive_pinmux_set_drive_type(pingroup, drive_type); + if (err < 0) + pr_err("pinmux: can't set pingroup %s driver type to %d: %d\n", + drive_pinmux_name(pingroup), + drive_type, err); } void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config, @@ -796,7 +829,8 @@ void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config, config[i].pull_down, config[i].pull_up, config[i].slew_rising, - config[i].slew_falling); + config[i].slew_falling, + config[i].drive_type); } void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config, |