diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2011-09-14 19:10:53 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-22 23:48:48 -0700 |
| commit | b03f4659a88520133bf6444023e76b8e423655f7 (patch) | |
| tree | a445bc8e823b0664ddf99f690c6cbc3fadc5f1de /arch/arm/mach-tegra/pinmux.c | |
| parent | bed4f0714457010cadf40049e3676d734634175d (diff) | |
Arm: Tegra: Cardhu: Set slew rise/fall rates properly
Setting the slewrise and slewfall rates properly.
Bug 811303
Reviewed-on: http://git-master/r/52367
(cherry picked from commit 337b90b5a359c4f320f58f5026fa511dca5d8031)
Change-Id: I518b4dcdad8ac338cf03d4fb6c634b0747a82836
Reviewed-on: http://git-master/r/62326
(cherry picked from commit 7a04424fb0b8c1f36f28c99f73a313cd192360e9)
Reviewed-on: http://git-master/r/63813
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Racfd777be42f83018a9e295e1c7048ebb02f7f9e
Diffstat (limited to 'arch/arm/mach-tegra/pinmux.c')
| -rw-r--r-- | arch/arm/mach-tegra/pinmux.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index 8d9038fd2261..413ecef978c4 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -773,8 +773,9 @@ static int tegra_drive_pinmux_set_slew_rising(int pg, spin_lock_irqsave(&mux_lock, flags); reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); - reg &= ~(0x3 << 28); - reg |= slew_rising << 28; + reg &= ~(drive_pingroups[pg].slewrise_mask << + drive_pingroups[pg].slewrise_offset); + reg |= slew_rising << drive_pingroups[pg].slewrise_offset; pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); spin_unlock_irqrestore(&mux_lock, flags); @@ -796,8 +797,9 @@ static int tegra_drive_pinmux_set_slew_falling(int pg, spin_lock_irqsave(&mux_lock, flags); reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); - reg &= ~(0x3 << 30); - reg |= slew_falling << 30; + reg &= ~(drive_pingroups[pg].slewfall_mask << + drive_pingroups[pg].slewfall_offset); + reg |= slew_falling << drive_pingroups[pg].slewfall_offset; pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); spin_unlock_irqrestore(&mux_lock, flags); |