diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2010-12-22 13:44:20 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:03 -0800 |
| commit | 59c211f7e1aa4c6f948c289419d3facdf687d92f (patch) | |
| tree | 3f12dc26508c43bf14e6db0b3cecbd9e111fb8ee /arch/arm/mach-tegra/platsmp.c | |
| parent | 191914c96cd231c067a2895db19e512423a6c7d9 (diff) | |
PARTIAL arm: tegra3: Add CPU idle support
Original-Change-Id: I5464b01ebb454b7fdc6fd316ba31de110a642063
Reviewed-on: http://git-master/r/14167
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I201cdb6dc4e78f762266cb96e48689d4d4f963f6
Rebase-Id: Rb3ac2fff9435330ec65c5541d369b743c9cb898f
Diffstat (limited to 'arch/arm/mach-tegra/platsmp.c')
| -rw-r--r-- | arch/arm/mach-tegra/platsmp.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 9f8c3c882f51..cd375d38d67d 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -36,8 +36,6 @@ (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340) #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \ (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344) -#define FLOW_CTRL_HALT_CPUx_EVENTS(cpu) \ - (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE + ((cpu)?(((cpu)-1)*8 + 0x14) : 0x0))) #define CPU_CLOCK(cpu) (0x1<<(8+cpu)) #define CPU_RESET(cpu) (0x1111ul<<(cpu)) @@ -80,7 +78,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) gic_secondary_init(0); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +int boot_secondary(unsigned int cpu, struct task_struct *idle) { u32 reg; int status; @@ -117,8 +115,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) CPU this will cause the flow controller to stop driving reset. The CPU will remain in reset because the clock and reset block is now driving reset. */ - writel(0, FLOW_CTRL_HALT_CPUx_EVENTS(cpu)); - dmb(); + flowctrl_writel(0, FLOW_CTRL_HALT_CPUx_EVENTS(cpu)); /* enable cpu clock on cpu */ reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); |